Lines Matching refs:csr
126 u32 csr; in read_fifo() local
138 csr = __raw_readl(creg); in read_fifo()
139 if ((csr & RX_DATA_READY) == 0) in read_fifo()
142 count = (csr & AT91_UDP_RXBYTECNT) >> 16; in read_fifo()
153 csr |= CLR_FX; in read_fifo()
156 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); in read_fifo()
159 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK1); in read_fifo()
163 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); in read_fifo()
164 __raw_writel(csr, creg); in read_fifo()
186 csr = __raw_readl(creg); in read_fifo()
200 u32 csr = __raw_readl(creg); in write_fifo() local
217 if (unlikely(csr & (AT91_UDP_TXCOMP | AT91_UDP_TXPKTRDY))) { in write_fifo()
218 if (csr & AT91_UDP_TXCOMP) { in write_fifo()
219 csr |= CLR_FX; in write_fifo()
220 csr &= ~(SET_FX | AT91_UDP_TXCOMP); in write_fifo()
221 __raw_writel(csr, creg); in write_fifo()
222 csr = __raw_readl(creg); in write_fifo()
224 if (csr & AT91_UDP_TXPKTRDY) in write_fifo()
253 csr &= ~SET_FX; in write_fifo()
254 csr |= CLR_FX | AT91_UDP_TXPKTRDY; in write_fifo()
255 __raw_writel(csr, creg); in write_fifo()
548 u32 csr; in at91_ep_set_halt() local
558 csr = __raw_readl(creg); in at91_ep_set_halt()
565 if (ep->is_in && (!list_empty(&ep->queue) || (csr >> 16) != 0)) in at91_ep_set_halt()
568 csr |= CLR_FX; in at91_ep_set_halt()
569 csr &= ~SET_FX; in at91_ep_set_halt()
571 csr |= AT91_UDP_FORCESTALL; in at91_ep_set_halt()
576 csr &= ~AT91_UDP_FORCESTALL; in at91_ep_set_halt()
578 __raw_writel(csr, creg); in at91_ep_set_halt()
811 u32 csr = __raw_readl(creg); in handle_ep() local
820 if (csr & (AT91_UDP_STALLSENT | AT91_UDP_TXCOMP)) { in handle_ep()
821 csr |= CLR_FX; in handle_ep()
822 csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP); in handle_ep()
823 __raw_writel(csr, creg); in handle_ep()
829 if (csr & AT91_UDP_STALLSENT) { in handle_ep()
833 csr |= CLR_FX; in handle_ep()
834 csr &= ~(SET_FX | AT91_UDP_STALLSENT); in handle_ep()
835 __raw_writel(csr, creg); in handle_ep()
836 csr = __raw_readl(creg); in handle_ep()
838 if (req && (csr & RX_DATA_READY)) in handle_ep()
849 static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr) in handle_setup() argument
859 rxcount = (csr & AT91_UDP_RXBYTECNT) >> 16; in handle_setup()
864 csr |= AT91_UDP_DIR; in handle_setup()
867 csr &= ~AT91_UDP_DIR; in handle_setup()
872 ERR("SETUP len %d, csr %08x\n", rxcount, csr); in handle_setup()
875 csr |= CLR_FX; in handle_setup()
876 csr &= ~(SET_FX | AT91_UDP_RXSETUP); in handle_setup()
877 __raw_writel(csr, creg); in handle_setup()
897 csr = __raw_readl(creg); in handle_setup()
898 csr |= CLR_FX; in handle_setup()
899 csr &= ~SET_FX; in handle_setup()
904 __raw_writel(csr | AT91_UDP_TXPKTRDY, creg); in handle_setup()
1060 csr |= AT91_UDP_FORCESTALL; in handle_setup()
1061 __raw_writel(csr, creg); in handle_setup()
1070 csr |= AT91_UDP_TXPKTRDY; in handle_setup()
1071 __raw_writel(csr, creg); in handle_setup()
1079 u32 csr = __raw_readl(creg); in handle_ep0() local
1082 if (unlikely(csr & AT91_UDP_STALLSENT)) { in handle_ep0()
1085 csr |= CLR_FX; in handle_ep0()
1086 csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_FORCESTALL); in handle_ep0()
1087 __raw_writel(csr, creg); in handle_ep0()
1089 csr = __raw_readl(creg); in handle_ep0()
1091 if (csr & AT91_UDP_RXSETUP) { in handle_ep0()
1094 handle_setup(udc, ep0, csr); in handle_ep0()
1104 if (csr & AT91_UDP_TXCOMP) { in handle_ep0()
1105 csr |= CLR_FX; in handle_ep0()
1106 csr &= ~(SET_FX | AT91_UDP_TXCOMP); in handle_ep0()
1123 __raw_writel(csr, creg); in handle_ep0()
1147 else if (csr & AT91_UDP_RX_DATA_BK0) { in handle_ep0()
1148 csr |= CLR_FX; in handle_ep0()
1149 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); in handle_ep0()
1157 csr = __raw_readl(creg); in handle_ep0()
1158 csr &= ~SET_FX; in handle_ep0()
1159 csr |= CLR_FX | AT91_UDP_TXPKTRDY; in handle_ep0()
1160 __raw_writel(csr, creg); in handle_ep0()
1182 __raw_writel(csr | AT91_UDP_FORCESTALL, creg); in handle_ep0()
1189 __raw_writel(csr, creg); in handle_ep0()