418 	u32 read_buf;  in smsc95xx_set_csums()  local
419 	int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf);  in smsc95xx_set_csums()
424 		read_buf |= Tx_COE_EN_;  in smsc95xx_set_csums()
426 		read_buf &= ~Tx_COE_EN_;  in smsc95xx_set_csums()
429 		read_buf |= Rx_COE_EN_;  in smsc95xx_set_csums()
431 		read_buf &= ~Rx_COE_EN_;  in smsc95xx_set_csums()
433 	ret = smsc95xx_write_reg(udev, COE_CR, read_buf);  in smsc95xx_set_csums()
437 	debug("COE_CR = 0x%08x\n", read_buf);  in smsc95xx_set_csums()
477 	u32 read_buf;  in smsc95xx_init_common()  local
493 		ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);  in smsc95xx_init_common()
498 	} while ((read_buf & HW_CFG_LRST_) && (timeout < 100));  in smsc95xx_init_common()
512 		ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf);  in smsc95xx_init_common()
517 	} while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));  in smsc95xx_init_common()
553 	ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf);  in smsc95xx_init_common()
556 	debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);  in smsc95xx_init_common()
558 	read_buf = DEFAULT_BULK_IN_DELAY;  in smsc95xx_init_common()
559 	ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf);  in smsc95xx_init_common()
563 	ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf);  in smsc95xx_init_common()
567 			"0x%08x\n", read_buf);  in smsc95xx_init_common()
569 	ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);  in smsc95xx_init_common()
572 	debug("Read Value from HW_CFG: 0x%08x\n", read_buf);  in smsc95xx_init_common()
575 	read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);  in smsc95xx_init_common()
577 	read_buf &= ~HW_CFG_RXDOFF_;  in smsc95xx_init_common()
580 	read_buf |= NET_IP_ALIGN << 9;  in smsc95xx_init_common()
582 	ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);  in smsc95xx_init_common()
586 	ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);  in smsc95xx_init_common()
589 	debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);  in smsc95xx_init_common()
596 	ret = smsc95xx_read_reg(udev, ID_REV, &read_buf);  in smsc95xx_init_common()
599 	debug("ID_REV = 0x%08x\n", read_buf);  in smsc95xx_init_common()
615 	read_buf = AFC_CFG_DEFAULT;  in smsc95xx_init_common()
616 	ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf);  in smsc95xx_init_common()
641 	ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf);  in smsc95xx_init_common()
646 	read_buf |= INT_EP_CTL_PHY_INT_;  in smsc95xx_init_common()
648 	ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf);  in smsc95xx_init_common()