149 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)  in dwc3_omap_read_utmi_status()  argument
151 	return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +  in dwc3_omap_read_utmi_status()
152 							omap->utmi_otg_offset);  in dwc3_omap_read_utmi_status()
155 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)  in dwc3_omap_write_utmi_status()  argument
157 	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +  in dwc3_omap_write_utmi_status()
158 					omap->utmi_otg_offset, value);  in dwc3_omap_write_utmi_status()
162 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)  in dwc3_omap_read_irq0_status()  argument
164 	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -  in dwc3_omap_read_irq0_status()
165 						omap->irq0_offset);  in dwc3_omap_read_irq0_status()
168 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)  in dwc3_omap_write_irq0_status()  argument
170 	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -  in dwc3_omap_write_irq0_status()
171 						omap->irq0_offset, value);  in dwc3_omap_write_irq0_status()
175 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)  in dwc3_omap_read_irqmisc_status()  argument
177 	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +  in dwc3_omap_read_irqmisc_status()
178 						omap->irqmisc_offset);  in dwc3_omap_read_irqmisc_status()
181 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)  in dwc3_omap_write_irqmisc_status()  argument
183 	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +  in dwc3_omap_write_irqmisc_status()
184 					omap->irqmisc_offset, value);  in dwc3_omap_write_irqmisc_status()
188 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)  in dwc3_omap_write_irqmisc_set()  argument
190 	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +  in dwc3_omap_write_irqmisc_set()
191 						omap->irqmisc_offset, value);  in dwc3_omap_write_irqmisc_set()
195 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)  in dwc3_omap_write_irq0_set()  argument
197 	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -  in dwc3_omap_write_irq0_set()
198 						omap->irq0_offset, value);  in dwc3_omap_write_irq0_set()
201 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)  in dwc3_omap_write_irqmisc_clr()  argument
203 	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +  in dwc3_omap_write_irqmisc_clr()
204 						omap->irqmisc_offset, value);  in dwc3_omap_write_irqmisc_clr()
207 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)  in dwc3_omap_write_irq0_clr()  argument
209 	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -  in dwc3_omap_write_irq0_clr()
210 						omap->irq0_offset, value);  in dwc3_omap_write_irq0_clr()
213 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,  in dwc3_omap_set_mailbox()  argument
220 		dev_dbg(omap->dev, "ID GND\n");  in dwc3_omap_set_mailbox()
222 		val = dwc3_omap_read_utmi_status(omap);  in dwc3_omap_set_mailbox()
228 		dwc3_omap_write_utmi_status(omap, val);  in dwc3_omap_set_mailbox()
232 		dev_dbg(omap->dev, "VBUS Connect\n");  in dwc3_omap_set_mailbox()
234 		val = dwc3_omap_read_utmi_status(omap);  in dwc3_omap_set_mailbox()
240 		dwc3_omap_write_utmi_status(omap, val);  in dwc3_omap_set_mailbox()
245 		dev_dbg(omap->dev, "VBUS Disconnect\n");  in dwc3_omap_set_mailbox()
247 		val = dwc3_omap_read_utmi_status(omap);  in dwc3_omap_set_mailbox()
253 		dwc3_omap_write_utmi_status(omap, val);  in dwc3_omap_set_mailbox()
257 		dev_dbg(omap->dev, "invalid state\n");  in dwc3_omap_set_mailbox()
263 	struct dwc3_omap	*omap = _omap;  in dwc3_omap_interrupt()  local
266 	reg = dwc3_omap_read_irqmisc_status(omap);  in dwc3_omap_interrupt()
269 		dev_dbg(omap->dev, "DMA Disable was Cleared\n");  in dwc3_omap_interrupt()
270 		omap->dma_status = false;  in dwc3_omap_interrupt()
274 		dev_dbg(omap->dev, "OTG Event\n");  in dwc3_omap_interrupt()
277 		dev_dbg(omap->dev, "DRVVBUS Rise\n");  in dwc3_omap_interrupt()
280 		dev_dbg(omap->dev, "CHRGVBUS Rise\n");  in dwc3_omap_interrupt()
283 		dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");  in dwc3_omap_interrupt()
286 		dev_dbg(omap->dev, "IDPULLUP Rise\n");  in dwc3_omap_interrupt()
289 		dev_dbg(omap->dev, "DRVVBUS Fall\n");  in dwc3_omap_interrupt()
292 		dev_dbg(omap->dev, "CHRGVBUS Fall\n");  in dwc3_omap_interrupt()
295 		dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");  in dwc3_omap_interrupt()
298 		dev_dbg(omap->dev, "IDPULLUP Fall\n");  in dwc3_omap_interrupt()
300 	dwc3_omap_write_irqmisc_status(omap, reg);  in dwc3_omap_interrupt()
302 	reg = dwc3_omap_read_irq0_status(omap);  in dwc3_omap_interrupt()
304 	dwc3_omap_write_irq0_status(omap, reg);  in dwc3_omap_interrupt()
309 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)  in dwc3_omap_enable_irqs()  argument
312 	dwc3_omap_write_irq0_set(omap, USBOTGSS_IRQO_COREIRQ_ST);  in dwc3_omap_enable_irqs()
314 	dwc3_omap_write_irqmisc_set(omap, USBOTGSS_INTERRUPTS);  in dwc3_omap_enable_irqs()
317 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)  in dwc3_omap_disable_irqs()  argument
320 	dwc3_omap_write_irq0_clr(omap, USBOTGSS_IRQO_COREIRQ_ST);  in dwc3_omap_disable_irqs()
322 	dwc3_omap_write_irqmisc_clr(omap, USBOTGSS_INTERRUPTS);  in dwc3_omap_disable_irqs()
325 static void dwc3_omap_map_offset(struct dwc3_omap *omap)  in dwc3_omap_map_offset()  argument
336 	omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;  in dwc3_omap_map_offset()
337 	omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;  in dwc3_omap_map_offset()
338 	omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;  in dwc3_omap_map_offset()
339 	omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;  in dwc3_omap_map_offset()
340 	omap->debug_offset = USBOTGSS_DEBUG_OFFSET;  in dwc3_omap_map_offset()
344 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap, int utmi_mode)  in dwc3_omap_set_utmi_mode()  argument
348 	reg = dwc3_omap_read_utmi_status(omap);  in dwc3_omap_set_utmi_mode()
358 		dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);  in dwc3_omap_set_utmi_mode()
361 	dwc3_omap_write_utmi_status(omap, reg);  in dwc3_omap_set_utmi_mode()
379 	struct dwc3_omap	*omap;  in dwc3_omap_uboot_init()  local
381 	omap = devm_kzalloc((struct udevice *)dev, sizeof(*omap), GFP_KERNEL);  in dwc3_omap_uboot_init()
382 	if (!omap)  in dwc3_omap_uboot_init()
385 	omap->base	= omap_dev->base;  in dwc3_omap_uboot_init()
386 	omap->index	= omap_dev->index;  in dwc3_omap_uboot_init()
388 	dwc3_omap_map_offset(omap);  in dwc3_omap_uboot_init()
389 	dwc3_omap_set_utmi_mode(omap, omap_dev->utmi_mode);  in dwc3_omap_uboot_init()
392 	reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);  in dwc3_omap_uboot_init()
393 	omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);  in dwc3_omap_uboot_init()
395 	dwc3_omap_set_mailbox(omap, omap_dev->vbus_id_status);  in dwc3_omap_uboot_init()
397 	dwc3_omap_enable_irqs(omap);  in dwc3_omap_uboot_init()
398 	list_add_tail(&omap->list, &dwc3_omap_list);  in dwc3_omap_uboot_init()
416 	struct dwc3_omap *omap = NULL;  in dwc3_omap_uboot_exit()  local
418 	list_for_each_entry(omap, &dwc3_omap_list, list) {  in dwc3_omap_uboot_exit()
419 		if (omap->index != index)  in dwc3_omap_uboot_exit()
422 		dwc3_omap_disable_irqs(omap);  in dwc3_omap_uboot_exit()
423 		list_del(&omap->list);  in dwc3_omap_uboot_exit()
424 		kfree(omap);  in dwc3_omap_uboot_exit()
440 	struct dwc3_omap *omap = NULL;  in dwc3_omap_uboot_interrupt_status()  local
442 	list_for_each_entry(omap, &dwc3_omap_list, list)  in dwc3_omap_uboot_interrupt_status()
443 		if (omap->index == index)  in dwc3_omap_uboot_interrupt_status()
444 			return dwc3_omap_interrupt(-1, omap);  in dwc3_omap_uboot_interrupt_status()