182 	ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);  in ufshcd_send_uic_cmd()
183 	ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);  in ufshcd_send_uic_cmd()
184 	ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);  in ufshcd_send_uic_cmd()
187 	ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,  in ufshcd_send_uic_cmd()
194 		ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);  in ufshcd_send_uic_cmd()
356 	ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);  in ufshcd_disable_intr_aggr()
374 	ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,  in ufshcd_enable_run_stop_reg()
376 	ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,  in ufshcd_enable_run_stop_reg()
395 	ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);  in ufshcd_enable_intr()
422 	ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl),  in ufshcd_make_hba_operational()
424 	ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl),  in ufshcd_make_hba_operational()
426 	ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl),  in ufshcd_make_hba_operational()
428 	ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl),  in ufshcd_make_hba_operational()
518 	ufshcd_writel(hba, CONTROLLER_DISABLE,  REG_CONTROLLER_ENABLE);  in ufshcd_hba_stop()
540 	ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);  in ufshcd_hba_start()
816 	ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);  in ufshcd_send_command()
822 		ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);  in ufshcd_send_command()
1916 	ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),  in ufshcd_probe()
1918 	ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);  in ufshcd_probe()