Lines Matching +full:0 +full:x10001

31 	TSHUT_MODE_CRU = 0,
38 * 0: low active, 1: high active
41 TSHUT_LOW_ACTIVE = 0,
51 ADC_DECREMENT = 0,
57 #define TSADCV2_USER_CON 0x00
58 #define TSADCV2_AUTO_CON 0x04
59 #define TSADCV2_INT_EN 0x08
60 #define TSADCV2_INT_PD 0x0c
61 #define TSADCV3_AUTO_SRC_CON 0x0c
62 #define TSADCV3_HT_INT_EN 0x14
63 #define TSADCV3_HSHUT_GPIO_INT_EN 0x18
64 #define TSADCV3_HSHUT_CRU_INT_EN 0x1c
65 #define TSADCV3_INT_PD 0x24
66 #define TSADCV3_HSHUT_PD 0x28
67 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
68 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
69 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
70 #define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04)
71 #define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04)
72 #define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04)
73 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
74 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
75 #define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c
76 #define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150
77 #define TSADCV2_AUTO_PERIOD 0x68
78 #define TSADCV2_AUTO_PERIOD_HT 0x6c
79 #define TSADCV3_AUTO_PERIOD 0x154
80 #define TSADCV3_AUTO_PERIOD_HT 0x158
81 #define TSADCV3_Q_MAX 0x210
83 #define TSADCV2_AUTO_EN BIT(0)
101 #define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff
103 #define TSADCV2_DATA_MASK 0xfff
104 #define TSADCV3_DATA_MASK 0x3ff
105 #define TSADCV4_DATA_MASK 0x1ff
106 #define TSADCV5_DATA_MASK 0x7ff
120 #define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */
123 #define TSADCV12_Q_MAX_VAL 0xfff /* 12bit 4095 */
124 #define TSADCV9_Q_MAX 0x210
125 #define TSADCV9_Q_MAX_VAL (0xffff0400 << 0)
127 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
128 #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
130 #define GRF_SARADC_TESTBIT 0x0e644
131 #define GRF_TSADC_TESTBIT_L 0x0e648
132 #define GRF_TSADC_TESTBIT_H 0x0e64c
134 #define PX30_GRF_SOC_CON0 0x0400
135 #define PX30_GRF_SOC_CON2 0x0408
137 #define RK3562_GRF_TSADC_CON 0x0580
139 #define RK3568_GRF_TSADC_CON 0x0600
140 #define RK3528_GRF_TSADC_CON 0x40030
141 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
142 #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
143 #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
144 #define RK3568_GRF_TSADC_TSEN (0x10001 << 8)
146 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
147 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
148 #define GRF_TSADC_VCM_EN_L (0x10001 << 7)
149 #define GRF_TSADC_VCM_EN_H (0x10001 << 7)
151 #define GRF_CON_TSADC_CH_INV (0x10001 << 1)
152 #define PX30S_TSADC_TDC_MODE (0x10001 << 4)
188 SENSOR_CPU = 0,
226 {0, MIN_TEMP},
236 {3519, 0},
267 {0, MIN_TEMP},
277 {629, 0},
318 {3728, 0},
347 {0, MAX_TEMP},
351 {0, MIN_TEMP},
360 {368, 0},
393 {0, MIN_TEMP},
403 {122, 0},
434 {0, MIN_TEMP},
444 {470, 0},
475 {0, MIN_TEMP},
485 {1486, 0},
516 {0, MIN_TEMP},
526 {1487, 0},
557 {0, MIN_TEMP},
567 {1856, 0},
598 {0, MIN_TEMP},
629 return 0; in tsadc_code_to_temp()
684 return 0; in tsadc_code_to_temp()
698 low = 0; in tsadc_temp_to_code_v2()
821 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, in tsadc_init_v2()
824 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, in tsadc_init_v2()
879 writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, in tsadc_init_v7()
882 writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, in tsadc_init_v7()
1214 priv->data->tsadc_get_temp(dev, 0, temp); in rockchip_thermal_get_temp()
1216 return 0; in rockchip_thermal_get_temp()
1224 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1248 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1289 if (ret < 0) { in rockchip_thermal_probe()
1307 if (priv->tshut_mode < 0) in rockchip_thermal_probe()
1313 if (priv->tshut_polarity < 0) in rockchip_thermal_probe()
1325 if (shut_temp < 0) in rockchip_thermal_probe()
1328 for (i = 0; i < tsadc->chn_num; i++) { in rockchip_thermal_probe()
1345 return 0; in rockchip_thermal_probe()
1355 return 0; in rockchip_thermal_ofdata_to_platdata()
1359 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1383 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1432 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1456 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1480 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1503 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1528 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1553 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1578 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1602 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1626 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1652 .chn_id = {0, 1, 2, 3, 4, 5, 6},