99 	u32 confr;  in zynq_spi_init_hw()  local
102 	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;  in zynq_spi_init_hw()
103 	writel(~confr, &regs->enr);  in zynq_spi_init_hw()
117 	confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |  in zynq_spi_init_hw()
119 	confr &= ~ZYNQ_SPI_CR_MSA_MASK;  in zynq_spi_init_hw()
120 	writel(confr, &regs->cr);  in zynq_spi_init_hw()
201 	u32 confr;  in zynq_spi_release_bus()  local
203 	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;  in zynq_spi_release_bus()
204 	writel(~confr, &regs->enr);  in zynq_spi_release_bus()
280 	uint32_t confr;  in zynq_spi_set_speed()  local
287 	confr = readl(&regs->cr);  in zynq_spi_set_speed()
298 	confr &= ~ZYNQ_SPI_CR_BAUD_MASK;  in zynq_spi_set_speed()
299 	confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);  in zynq_spi_set_speed()
301 	writel(confr, &regs->cr);  in zynq_spi_set_speed()
314 	uint32_t confr;  in zynq_spi_set_mode()  local
317 	confr = readl(&regs->cr);  in zynq_spi_set_mode()
318 	confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);  in zynq_spi_set_mode()
321 		confr |= ZYNQ_SPI_CR_CPHA_MASK;  in zynq_spi_set_mode()
323 		confr |= ZYNQ_SPI_CR_CPOL_MASK;  in zynq_spi_set_mode()
325 	writel(confr, &regs->cr);  in zynq_spi_set_mode()