123 	u32 confr;  in zynq_qspi_init_hw()  local
143 	confr = readl(&regs->cr);  in zynq_qspi_init_hw()
144 	confr &= ~ZYNQ_QSPI_CR_MSA_MASK;  in zynq_qspi_init_hw()
145 	confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |  in zynq_qspi_init_hw()
148 	writel(confr, &regs->cr);  in zynq_qspi_init_hw()
151 	confr = readl(&regs->lqspicfg);  in zynq_qspi_init_hw()
152 	confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;  in zynq_qspi_init_hw()
153 	writel(confr, &regs->lqspicfg);  in zynq_qspi_init_hw()
269 	u32 confr;  in zynq_qspi_chipselect()  local
272 	confr = readl(&regs->cr);  in zynq_qspi_chipselect()
276 		confr &= ~ZYNQ_QSPI_CR_SS_MASK;  in zynq_qspi_chipselect()
277 		confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &  in zynq_qspi_chipselect()
281 		confr |= ZYNQ_QSPI_CR_SS_MASK;  in zynq_qspi_chipselect()
283 	writel(confr, &regs->cr);  in zynq_qspi_chipselect()
555 	uint32_t confr;  in zynq_qspi_set_speed()  local
562 	confr = readl(&regs->cr);  in zynq_qspi_set_speed()
574 	confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;  in zynq_qspi_set_speed()
575 	confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);  in zynq_qspi_set_speed()
577 	writel(confr, &regs->cr);  in zynq_qspi_set_speed()
589 	uint32_t confr;  in zynq_qspi_set_mode()  local
592 	confr = readl(&regs->cr);  in zynq_qspi_set_mode()
593 	confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);  in zynq_qspi_set_mode()
596 		confr |= ZYNQ_QSPI_CR_CPHA_MASK;  in zynq_qspi_set_mode()
598 		confr |= ZYNQ_QSPI_CR_CPOL_MASK;  in zynq_qspi_set_mode()
600 	writel(confr, &regs->cr);  in zynq_qspi_set_mode()