34 #define QSPI_CLK_DIV_MAX                0xffff
50 #define QSPI_BUSY                       BIT(0)
53 #define MM_SWITCH                       0x01
55 #define MEM_CS_UNSELECT                 0xfffff8ff
56 #define MMAP_START_ADDR_DRA		0x5c000000
57 #define MMAP_START_ADDR_AM43x		0x30000000
58 #define CORE_CTRL_IO                    0x4a002558
60 #define QSPI_CMD_READ                   (0x3 << 0)
61 #define QSPI_CMD_READ_DUAL		(0x6b << 0)
62 #define QSPI_CMD_READ_QUAD              (0x6c << 0)
63 #define QSPI_CMD_READ_FAST              (0x0b << 0)
64 #define QSPI_SETUP0_NUM_A_BYTES         (0x3 << 8)
65 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
66 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS  (0x1 << 10)
67 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
68 #define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
69 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
70 #define QSPI_CMD_WRITE                  (0x12 << 16)
71 #define QSPI_NUM_DUMMY_BITS             (0x0 << 24)
122 		clk_div = 0;  in ti_spi_set_speed()
148 	priv->dc = 0;  in __ti_qspi_set_mode()
150 		priv->dc |= QSPI_CKPHA(0);  in __ti_qspi_set_mode()
152 		priv->dc |= QSPI_CKPOL(0);  in __ti_qspi_set_mode()
154 		priv->dc |= QSPI_CSPOL(0);  in __ti_qspi_set_mode()
156 	return 0;  in __ti_qspi_set_mode()
162 	writel(0, &priv->base->cmd);  in __ti_qspi_claim_bus()
163 	writel(0, &priv->base->data);  in __ti_qspi_claim_bus()
168 	return 0;  in __ti_qspi_claim_bus()
173 	writel(0, &priv->base->dc);  in __ti_qspi_release_bus()
174 	writel(0, &priv->base->cmd);  in __ti_qspi_release_bus()
175 	writel(0, &priv->base->data);  in __ti_qspi_release_bus()
205 		return 0;  in __ti_qspi_xfer()
210 		return 0;  in __ti_qspi_xfer()
213 	if (bitlen == 0)  in __ti_qspi_xfer()
222 	priv->cmd = 0;  in __ti_qspi_xfer()
227 	priv->cmd |= 0xfff;  in __ti_qspi_xfer()
230 		u8 xfer_len = 0;  in __ti_qspi_xfer()
260 				if (--timeout < 0) {  in __ti_qspi_xfer()
276 				if (--timeout < 0) {  in __ti_qspi_xfer()
294 	return 0;  in __ti_qspi_xfer()
351 	u32 memval = 0;  in ti_spi_setup_spi_register()
448 		writel(0, &priv->base->setup0);  in __ti_qspi_setup_memorymap()
483 	return 0;  in ti_qspi_set_speed()
524 	return 0;  in ti_qspi_release_bus()
551 	return 0;  in ti_qspi_probe()
584 	return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);  in map_syscon_chipselects()
589 		map_physmem(addr, 0, MAP_NOCACHE);  in map_syscon_chipselects()
602 	priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0,  in ti_qspi_ofdata_to_platdata()
606 	if (priv->max_hz < 0) {  in ti_qspi_ofdata_to_platdata()
612 	debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,  in ti_qspi_ofdata_to_platdata()
615 	return 0;  in ti_qspi_ofdata_to_platdata()
625 	return 0;  in ti_qspi_child_pre_probe()