Lines Matching full:sfc
158 /* The SFC can transfer max 16KB - 1 at one time
194 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) in rockchip_sfc_reset() argument
199 writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); in rockchip_sfc_reset()
201 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, in rockchip_sfc_reset()
205 printf("SFC reset never finished\n"); in rockchip_sfc_reset()
208 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); in rockchip_sfc_reset()
213 static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) in rockchip_sfc_get_version() argument
215 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); in rockchip_sfc_get_version()
218 static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) in rockchip_sfc_get_max_iosize() argument
220 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) in rockchip_sfc_get_max_iosize()
226 static u32 rockchip_sfc_get_max_dll_cells(struct rockchip_sfc *sfc) in rockchip_sfc_get_max_dll_cells() argument
228 switch (rockchip_sfc_get_version(sfc)) { in rockchip_sfc_get_max_dll_cells()
240 static __maybe_unused void rockchip_sfc_set_delay_lines(struct rockchip_sfc *sfc, u16 cells) in rockchip_sfc_set_delay_lines() argument
242 u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc); in rockchip_sfc_set_delay_lines()
251 writel(val, sfc->regbase + SFC_DLL_CTRL0); in rockchip_sfc_set_delay_lines()
254 static int rockchip_sfc_init(struct rockchip_sfc *sfc) in rockchip_sfc_init() argument
256 writel(0, sfc->regbase + SFC_CTRL); in rockchip_sfc_init()
257 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) in rockchip_sfc_init()
258 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); in rockchip_sfc_init()
265 struct rockchip_sfc *sfc = dev_get_platdata(bus); in rockchip_sfc_ofdata_to_platdata() local
267 sfc->regbase = dev_read_addr_ptr(bus); in rockchip_sfc_ofdata_to_platdata()
268 if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma")) in rockchip_sfc_ofdata_to_platdata()
269 sfc->use_dma = false; in rockchip_sfc_ofdata_to_platdata()
271 sfc->use_dma = true; in rockchip_sfc_ofdata_to_platdata()
275 ret = clk_get_by_index(bus, 0, &sfc->clk); in rockchip_sfc_ofdata_to_platdata()
281 ret = clk_get_by_index(bus, 1, &sfc->hclk); in rockchip_sfc_ofdata_to_platdata()
293 struct rockchip_sfc *sfc = dev_get_platdata(bus); in rockchip_sfc_probe() local
297 ret = clk_enable(&sfc->hclk); in rockchip_sfc_probe()
299 dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret); in rockchip_sfc_probe()
301 ret = clk_enable(&sfc->clk); in rockchip_sfc_probe()
303 dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret); in rockchip_sfc_probe()
306 ret = rockchip_sfc_init(sfc); in rockchip_sfc_probe()
310 sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); in rockchip_sfc_probe()
311 sfc->version = rockchip_sfc_get_version(sfc); in rockchip_sfc_probe()
312 sfc->max_freq = SFC_MAX_SPEED; in rockchip_sfc_probe()
313 sfc->dev = bus; in rockchip_sfc_probe()
319 clk_disable(&sfc->clk); in rockchip_sfc_probe()
320 clk_disable(&sfc->hclk); in rockchip_sfc_probe()
326 static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) in rockchip_sfc_wait_txfifo_ready() argument
331 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, in rockchip_sfc_wait_txfifo_ready()
335 dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n"); in rockchip_sfc_wait_txfifo_ready()
343 static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) in rockchip_sfc_wait_rxfifo_ready() argument
348 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, in rockchip_sfc_wait_rxfifo_ready()
352 dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n"); in rockchip_sfc_wait_rxfifo_ready()
364 * SFC not support output DUMMY cycles right after CMD cycles, so in rockchip_sfc_adjust_op_work()
375 static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout) in rockchip_sfc_wait_for_dma_finished() argument
381 while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) { in rockchip_sfc_wait_for_dma_finished()
384 rockchip_sfc_reset(sfc); in rockchip_sfc_wait_for_dma_finished()
392 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); in rockchip_sfc_wait_for_dma_finished()
397 static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, in rockchip_sfc_xfer_setup() argument
402 struct dm_spi_slave_platdata *plat = dev_get_platdata(sfc->dev); in rockchip_sfc_xfer_setup()
417 writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT); in rockchip_sfc_xfer_setup()
434 if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ in rockchip_sfc_xfer_setup()
435 writel(len, sfc->regbase + SFC_LEN_EXT); in rockchip_sfc_xfer_setup()
451 dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", in rockchip_sfc_xfer_setup()
454 dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n", in rockchip_sfc_xfer_setup()
457 writel(ctrl, sfc->regbase + SFC_CTRL); in rockchip_sfc_xfer_setup()
458 writel(cmd, sfc->regbase + SFC_CMD); in rockchip_sfc_xfer_setup()
460 writel(op->addr.val, sfc->regbase + SFC_ADDR); in rockchip_sfc_xfer_setup()
465 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) in rockchip_sfc_write_fifo() argument
475 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); in rockchip_sfc_write_fifo()
479 writesl(sfc->regbase + SFC_DATA, buf, write_words); in rockchip_sfc_write_fifo()
486 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); in rockchip_sfc_write_fifo()
490 writel(tmp, sfc->regbase + SFC_DATA); in rockchip_sfc_write_fifo()
496 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) in rockchip_sfc_read_fifo() argument
507 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); in rockchip_sfc_read_fifo()
511 readsl(sfc->regbase + SFC_DATA, buf, read_words); in rockchip_sfc_read_fifo()
518 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); in rockchip_sfc_read_fifo()
521 tmp = readl(sfc->regbase + SFC_DATA); in rockchip_sfc_read_fifo()
528 static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) in rockchip_sfc_fifo_transfer_dma() argument
530 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); in rockchip_sfc_fifo_transfer_dma()
531 writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); in rockchip_sfc_fifo_transfer_dma()
532 writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); in rockchip_sfc_fifo_transfer_dma()
537 static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, in rockchip_sfc_xfer_data_poll() argument
540 dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); in rockchip_sfc_xfer_data_poll()
543 return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); in rockchip_sfc_xfer_data_poll()
545 return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); in rockchip_sfc_xfer_data_poll()
548 static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, in rockchip_sfc_xfer_data_dma() argument
556 dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); in rockchip_sfc_xfer_data_dma()
570 ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len); in rockchip_sfc_xfer_data_dma()
571 rockchip_sfc_wait_for_dma_finished(sfc, len * 10); in rockchip_sfc_xfer_data_dma()
577 static int rockchip_sfc_xfer_data_dma_async(struct rockchip_sfc *sfc, in rockchip_sfc_xfer_data_dma_async() argument
590 dev_dbg(sfc->dev, "xfer_dma_async len=%x %p\n", len, dma_buf); in rockchip_sfc_xfer_data_dma_async()
592 rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)dma_buf, len); in rockchip_sfc_xfer_data_dma_async()
593 sfc->last_async_size = len; in rockchip_sfc_xfer_data_dma_async()
598 static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) in rockchip_sfc_xfer_done() argument
603 ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, in rockchip_sfc_xfer_done()
607 dev_err(sfc->dev, "wait sfc idle timeout\n"); in rockchip_sfc_xfer_done()
608 rockchip_sfc_reset(sfc); in rockchip_sfc_xfer_done()
619 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); in rockchip_sfc_exec_op() local
620 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); in rockchip_sfc_exec_op()
624 if (sfc->last_async_size) { in rockchip_sfc_exec_op()
625 rockchip_sfc_wait_for_dma_finished(sfc, sfc->last_async_size); in rockchip_sfc_exec_op()
626 sfc->last_async_size = 0; in rockchip_sfc_exec_op()
629 rockchip_sfc_xfer_setup(sfc, mem, op, len); in rockchip_sfc_exec_op()
631 if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) { in rockchip_sfc_exec_op()
633 return rockchip_sfc_xfer_data_dma_async(sfc, op, len); in rockchip_sfc_exec_op()
634 ret = rockchip_sfc_xfer_data_dma(sfc, op, len); in rockchip_sfc_exec_op()
636 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); in rockchip_sfc_exec_op()
640 dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); in rockchip_sfc_exec_op()
646 return rockchip_sfc_xfer_done(sfc, 100000); in rockchip_sfc_exec_op()
651 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); in rockchip_sfc_adjust_op_size() local
653 op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); in rockchip_sfc_adjust_op_size()
659 static int rockchip_sfc_exec_op_bypass(struct rockchip_sfc *sfc, in rockchip_sfc_exec_op_bypass() argument
663 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); in rockchip_sfc_exec_op_bypass()
667 rockchip_sfc_xfer_setup(sfc, mem, op, len); in rockchip_sfc_exec_op_bypass()
668 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); in rockchip_sfc_exec_op_bypass()
670 dev_err(sfc->dev, "xfer data failed ret %d\n", ret); in rockchip_sfc_exec_op_bypass()
675 return rockchip_sfc_xfer_done(sfc, 100000); in rockchip_sfc_exec_op_bypass()
678 static void rockchip_sfc_delay_lines_tuning(struct rockchip_sfc *sfc, struct spi_slave *mem) in rockchip_sfc_delay_lines_tuning() argument
685 u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc); in rockchip_sfc_delay_lines_tuning()
690 clk_set_rate(&sfc->clk, SFC_DLL_THRESHOLD_RATE); in rockchip_sfc_delay_lines_tuning()
692 rockchip_sfc_exec_op_bypass(sfc, mem, &op); in rockchip_sfc_delay_lines_tuning()
695 dev_dbg(sfc->dev, "no dev, dll by pass\n"); in rockchip_sfc_delay_lines_tuning()
696 clk_set_rate(&sfc->clk, sfc->speed); in rockchip_sfc_delay_lines_tuning()
701 clk_set_rate(&sfc->clk, sfc->speed); in rockchip_sfc_delay_lines_tuning()
706 rockchip_sfc_set_delay_lines(sfc, right); in rockchip_sfc_delay_lines_tuning()
707 rockchip_sfc_exec_op_bypass(sfc, mem, &op); in rockchip_sfc_delay_lines_tuning()
708 dev_dbg(sfc->dev, "dll read flash id:%x %x %x\n", in rockchip_sfc_delay_lines_tuning()
732 sfc->dll_cells = left + (right - left) * 2 / 5; in rockchip_sfc_delay_lines_tuning()
734 sfc->dll_cells = left + (right - left) / 2; in rockchip_sfc_delay_lines_tuning()
736 sfc->dll_cells = 0; in rockchip_sfc_delay_lines_tuning()
739 if (sfc->dll_cells) { in rockchip_sfc_delay_lines_tuning()
740 dev_dbg(sfc->dev, "%d %d %d dll training success in %dMHz max_cells=%u sfc_ver=%d\n", in rockchip_sfc_delay_lines_tuning()
741 left, right, sfc->dll_cells, sfc->speed, in rockchip_sfc_delay_lines_tuning()
742 rockchip_sfc_get_max_dll_cells(sfc), rockchip_sfc_get_version(sfc)); in rockchip_sfc_delay_lines_tuning()
743 rockchip_sfc_set_delay_lines(sfc, (u16)sfc->dll_cells); in rockchip_sfc_delay_lines_tuning()
745 dev_err(sfc->dev, "%d %d dll training failed in %dMHz, reduce the speed\n", in rockchip_sfc_delay_lines_tuning()
746 left, right, sfc->speed); in rockchip_sfc_delay_lines_tuning()
747 rockchip_sfc_set_delay_lines(sfc, 0); in rockchip_sfc_delay_lines_tuning()
748 clk_set_rate(&sfc->clk, SFC_DLL_THRESHOLD_RATE); in rockchip_sfc_delay_lines_tuning()
749 sfc->speed = clk_get_rate(&sfc->clk); in rockchip_sfc_delay_lines_tuning()
757 struct rockchip_sfc *sfc = dev_get_platdata(bus); in rockchip_sfc_set_speed() local
759 if (speed > sfc->max_freq) in rockchip_sfc_set_speed()
760 speed = sfc->max_freq; in rockchip_sfc_set_speed()
762 if (speed == sfc->speed) in rockchip_sfc_set_speed()
766 int ret = clk_set_rate(&sfc->clk, speed); in rockchip_sfc_set_speed()
769 dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n", in rockchip_sfc_set_speed()
773 sfc->speed = speed; in rockchip_sfc_set_speed()
774 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) { in rockchip_sfc_set_speed()
775 if (clk_get_rate(&sfc->clk) > SFC_DLL_THRESHOLD_RATE) in rockchip_sfc_set_speed()
776 rockchip_sfc_delay_lines_tuning(sfc, NULL); in rockchip_sfc_set_speed()
778 rockchip_sfc_set_delay_lines(sfc, 0); in rockchip_sfc_set_speed()
781 dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n", in rockchip_sfc_set_speed()
782 sfc->speed, clk_get_rate(&sfc->clk)); in rockchip_sfc_set_speed()
784 dev_dbg(sfc->dev, "sfc failed, CLK not support\n"); in rockchip_sfc_set_speed()
806 { .compatible = "rockchip,sfc"},