28 #define DEBUG_RK_SPI	0
63 #define SPI_CR0_RSD_MAX		0x3
86 	writel(enable ? 1 : 0, &regs->enr);  in rkspi_enable_chip()
104 	if (clk_div > 0xfffe) {  in rkspi_set_clk()
105 		clk_div = 0xfffe;  in rkspi_set_clk()
111 	clk_div = (clk_div + 1) & 0xfffe;  in rkspi_set_clk()
121 	clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);  in rkspi_set_clk()
129 	start = get_timer(0);  in rkspi_wait_till_not_busy()
137 	return 0;  in rkspi_wait_till_not_busy()
169 	writel(0, &regs->ser);  in spi_cs_deactivate()
184 	plat->base = dtplat->reg[0];  in conv_of_platdata()
186 	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);  in conv_of_platdata()
187 	if (ret < 0)  in conv_of_platdata()
189 	dev->req_seq = 0;  in conv_of_platdata()
191 	return 0;  in conv_of_platdata()
205 	ret = clk_get_by_index(bus, 0, &priv->clk);  in rockchip_spi_ofdata_to_platdata()
206 	if (ret < 0) {  in rockchip_spi_ofdata_to_platdata()
215 		dev_read_u32_default(bus, "spi-deactivate-delay", 0);  in rockchip_spi_ofdata_to_platdata()
217 		dev_read_u32_default(bus, "spi-activate-delay", 0);  in rockchip_spi_ofdata_to_platdata()
219 	rsd_nsecs = dev_read_u32_default(bus, "rx-sample-delay-ns", 0);  in rockchip_spi_ofdata_to_platdata()
220 	if (rsd_nsecs > 0) {  in rockchip_spi_ofdata_to_platdata()
241 	return 0;  in rockchip_spi_ofdata_to_platdata()
297 	if (ret < 0) {  in rockchip_spi_probe()
308 	return 0;  in rockchip_spi_probe()
320 	rkspi_enable_chip(regs, 0);  in rockchip_spi_claim_bus()
348 	/* set SPI mode 0..3 */  in rockchip_spi_claim_bus()
380 	return 0;  in rockchip_spi_claim_bus()
397 	return 0;  in rockchip_spi_config()
407 	return 0;  in rockchip_spi_release_bus()
434 	while (len > 0) {  in rockchip_spi_xfer()
435 		int todo = min(len, 0xffff);  in rockchip_spi_xfer()
448 					writel(out ? *out++ : 0, regs->txdr);  in rockchip_spi_xfer()
484 	return 0;  in rockchip_spi_set_speed()
493 	return 0;  in rockchip_spi_set_mode()