Lines Matching refs:ctlr
86 static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) in ich_set_bbar() argument
92 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; in ich_set_bbar()
94 ich_writel(ctlr, ichspi_bbar, ctlr->bbar); in ich_set_bbar()
116 struct ich_spi_priv *ctlr) in ich_init_controller() argument
129 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); in ich_init_controller()
130 ctlr->menubytes = sizeof(ich7_spi->opmenu); in ich_init_controller()
131 ctlr->optype = offsetof(struct ich7_spi_regs, optype); in ich_init_controller()
132 ctlr->addr = offsetof(struct ich7_spi_regs, spia); in ich_init_controller()
133 ctlr->data = offsetof(struct ich7_spi_regs, spid); in ich_init_controller()
134 ctlr->databytes = sizeof(ich7_spi->spid); in ich_init_controller()
135 ctlr->status = offsetof(struct ich7_spi_regs, spis); in ich_init_controller()
136 ctlr->control = offsetof(struct ich7_spi_regs, spic); in ich_init_controller()
137 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); in ich_init_controller()
138 ctlr->preop = offsetof(struct ich7_spi_regs, preop); in ich_init_controller()
139 ctlr->base = ich7_spi; in ich_init_controller()
143 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); in ich_init_controller()
144 ctlr->menubytes = sizeof(ich9_spi->opmenu); in ich_init_controller()
145 ctlr->optype = offsetof(struct ich9_spi_regs, optype); in ich_init_controller()
146 ctlr->addr = offsetof(struct ich9_spi_regs, faddr); in ich_init_controller()
147 ctlr->data = offsetof(struct ich9_spi_regs, fdata); in ich_init_controller()
148 ctlr->databytes = sizeof(ich9_spi->fdata); in ich_init_controller()
149 ctlr->status = offsetof(struct ich9_spi_regs, ssfs); in ich_init_controller()
150 ctlr->control = offsetof(struct ich9_spi_regs, ssfc); in ich_init_controller()
151 ctlr->speed = ctlr->control + 2; in ich_init_controller()
152 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); in ich_init_controller()
153 ctlr->preop = offsetof(struct ich9_spi_regs, preop); in ich_init_controller()
154 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); in ich_init_controller()
155 ctlr->pr = &ich9_spi->pr[0]; in ich_init_controller()
156 ctlr->base = ich9_spi; in ich_init_controller()
164 ctlr->max_speed = 20000000; in ich_init_controller()
166 ctlr->max_speed = 33000000; in ich_init_controller()
168 plat->ich_version, ctlr->base, ctlr->max_speed); in ich_init_controller()
170 ich_set_bbar(ctlr, 0); in ich_init_controller()
250 static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans, in spi_setup_opcode() argument
254 uint8_t opmenu[ctlr->menubytes]; in spi_setup_opcode()
260 ich_writeb(ctlr, trans->opcode, ctlr->opmenu); in spi_setup_opcode()
261 optypes = ich_readw(ctlr, ctlr->optype); in spi_setup_opcode()
263 ich_writew(ctlr, optypes, ctlr->optype); in spi_setup_opcode()
274 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu)); in spi_setup_opcode()
275 for (opcode_index = 0; opcode_index < ctlr->menubytes; in spi_setup_opcode()
281 if (opcode_index == ctlr->menubytes) { in spi_setup_opcode()
287 optypes = ich_readw(ctlr, ctlr->optype); in spi_setup_opcode()
331 static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask, in ich_status_poll() argument
338 status = ich_readw(ctlr, ctlr->status); in ich_status_poll()
341 ich_writew(ctlr, status & bitmask, in ich_status_poll()
342 ctlr->status); in ich_status_poll()
356 struct ich_spi_priv *ctlr = dev_get_priv(dev); in ich_spi_config_opcode() local
363 ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop); in ich_spi_config_opcode()
364 ich_writew(ctlr, SPI_OPTYPE, ctlr->optype); in ich_spi_config_opcode()
365 ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu); in ich_spi_config_opcode()
366 ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32)); in ich_spi_config_opcode()
374 struct ich_spi_priv *ctlr = dev_get_priv(bus); in ich_spi_xfer() local
380 struct spi_trans *trans = &ctlr->trans; in ich_spi_xfer()
383 bool lock = spi_lock_status(plat, ctlr->base); in ich_spi_xfer()
437 ret = ich_status_poll(ctlr, SPIS_SCIP, 0); in ich_spi_xfer()
442 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); in ich_spi_xfer()
444 ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); in ich_spi_xfer()
447 opcode_index = spi_setup_opcode(ctlr, trans, lock); in ich_spi_xfer()
461 ich_writew(ctlr, trans->opcode, ctlr->preop); in ich_spi_xfer()
465 if (ctlr->speed && ctlr->max_speed >= 33000000) { in ich_spi_xfer()
468 byte = ich_readb(ctlr, ctlr->speed); in ich_spi_xfer()
469 if (ctlr->cur_speed >= 33000000) in ich_spi_xfer()
473 ich_writeb(ctlr, byte, ctlr->speed); in ich_spi_xfer()
487 if (ich_readw(ctlr, ctlr->preop)) in ich_spi_xfer()
493 ich_writel(ctlr, trans->offset & 0x00FFFFFF, in ich_spi_xfer()
494 ctlr->addr); in ich_spi_xfer()
502 ich_writew(ctlr, control, ctlr->control); in ich_spi_xfer()
505 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); in ich_spi_xfer()
524 if (trans->bytesout > ctlr->databytes) { in ich_spi_xfer()
537 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr); in ich_spi_xfer()
540 data_length = min(trans->bytesout, ctlr->databytes); in ich_spi_xfer()
542 data_length = min(trans->bytesin, ctlr->databytes); in ich_spi_xfer()
546 write_reg(ctlr, trans->out, ctlr->data, data_length); in ich_spi_xfer()
553 control &= ~((ctlr->databytes - 1) << 8); in ich_spi_xfer()
558 ich_writew(ctlr, control, ctlr->control); in ich_spi_xfer()
561 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); in ich_spi_xfer()
571 read_reg(ctlr, ctlr->data, trans->in, data_length); in ich_spi_xfer()
580 ich_writew(ctlr, 0, ctlr->preop); in ich_spi_xfer()