Lines Matching +full:rx +full:- +full:ctrl
2 * (C) Copyright 2000-2003
5 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
10 * SPDX-License-Identifier: GPL-2.0+
40 /* tx/rx data wait timeout value, unit: us */
43 /* CTAR register pre-configure value */
52 /* CTAR register pre-configure mask */
62 * struct fsl_dspi_platdata - platform data for Freescale DSPI
77 * struct fsl_dspi_priv - private data for Freescale DSPI
137 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr); in dspi_halt()
144 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val); in dspi_halt()
152 dspi_write32(priv->flags, &priv->regs->mcr, cfg_val); in fsl_dspi_init_mcr()
157 priv->mcr_val = cfg_val; in fsl_dspi_init_mcr()
167 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr); in fsl_dspi_cfg_cs_active_state()
174 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val); in fsl_dspi_cfg_cs_active_state()
184 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]); in fsl_dspi_cfg_ctar_mode()
187 bus_setup |= priv->ctar_val[cs]; in fsl_dspi_cfg_ctar_mode()
197 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup); in fsl_dspi_cfg_ctar_mode()
199 priv->charbit = in fsl_dspi_cfg_ctar_mode()
200 ((dspi_read32(priv->flags, &priv->regs->ctar[0]) & in fsl_dspi_cfg_ctar_mode()
211 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr); in fsl_dspi_clr_fifo()
212 /* flush RX and TX FIFO */ in fsl_dspi_clr_fifo()
214 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val); in fsl_dspi_clr_fifo()
218 static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data) in dspi_tx() argument
223 while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 && in dspi_tx()
224 timeout--) in dspi_tx()
228 dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data)); in dspi_tx()
238 while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 && in dspi_rx()
239 timeout--) in dspi_rx()
244 dspi_read32(priv->flags, &priv->regs->rfr)); in dspi_rx()
256 static u32 ctrl; in dspi_xfer() local
259 if (priv->charbit == 16) { in dspi_xfer()
269 ctrl |= DSPI_TFR_CONT; in dspi_xfer()
271 ctrl = ctrl & DSPI_TFR_CONT; in dspi_xfer()
272 ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs); in dspi_xfer()
275 int tmp_len = len - 1; in dspi_xfer()
276 while (tmp_len--) { in dspi_xfer()
278 if (priv->charbit == 16) in dspi_xfer()
279 dspi_tx(priv, ctrl, *spi_wr16++); in dspi_xfer()
281 dspi_tx(priv, ctrl, *spi_wr++); in dspi_xfer()
286 dspi_tx(priv, ctrl, DSPI_IDLE_VAL); in dspi_xfer()
287 if (priv->charbit == 16) in dspi_xfer()
298 ctrl &= ~DSPI_TFR_CONT; in dspi_xfer()
302 if (priv->charbit == 16) in dspi_xfer()
303 dspi_tx(priv, ctrl, *spi_wr16); in dspi_xfer()
305 dspi_tx(priv, ctrl, *spi_wr); in dspi_xfer()
310 dspi_tx(priv, ctrl, DSPI_IDLE_VAL); in dspi_xfer()
311 if (priv->charbit == 16) in dspi_xfer()
318 dspi_tx(priv, ctrl, DSPI_IDLE_VAL); in dspi_xfer()
338 /* Valid baud rate pre-scaler values */ in fsl_dspi_hz_to_spi_baud()
360 *pbr = ARRAY_SIZE(pbr_tbl) - 1; in fsl_dspi_hz_to_spi_baud()
361 *br = ARRAY_SIZE(brs) - 1; in fsl_dspi_hz_to_spi_baud()
362 return -EINVAL; in fsl_dspi_hz_to_spi_baud()
371 bus_clk = priv->bus_clk; in fsl_dspi_cfg_speed()
376 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]); in fsl_dspi_cfg_speed()
381 speed = priv->speed_hz; in fsl_dspi_cfg_speed()
387 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup); in fsl_dspi_cfg_speed()
389 priv->speed_hz = speed; in fsl_dspi_cfg_speed()
420 dspi->priv.flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG; in spi_setup_slave()
423 dspi->priv.regs = (struct dspi *)MMAP_DSPI; in spi_setup_slave()
426 dspi->priv.bus_clk = gd->bus_clk; in spi_setup_slave()
428 dspi->priv.bus_clk = mxc_get_clock(MXC_DSPI_CLK); in spi_setup_slave()
430 dspi->priv.speed_hz = FSL_DSPI_DEFAULT_SCK_FREQ; in spi_setup_slave()
435 fsl_dspi_init_mcr(&dspi->priv, mcr_cfg_val); in spi_setup_slave()
438 dspi->priv.ctar_val[i] = DSPI_CTAR_DEFAULT_VALUE; in spi_setup_slave()
442 dspi->priv.ctar_val[0] = CONFIG_SYS_DSPI_CTAR0; in spi_setup_slave()
446 dspi->priv.ctar_val[1] = CONFIG_SYS_DSPI_CTAR1; in spi_setup_slave()
450 dspi->priv.ctar_val[2] = CONFIG_SYS_DSPI_CTAR2; in spi_setup_slave()
454 dspi->priv.ctar_val[3] = CONFIG_SYS_DSPI_CTAR3; in spi_setup_slave()
458 dspi->priv.ctar_val[4] = CONFIG_SYS_DSPI_CTAR4; in spi_setup_slave()
462 dspi->priv.ctar_val[5] = CONFIG_SYS_DSPI_CTAR5; in spi_setup_slave()
466 dspi->priv.ctar_val[6] = CONFIG_SYS_DSPI_CTAR6; in spi_setup_slave()
470 dspi->priv.ctar_val[7] = CONFIG_SYS_DSPI_CTAR7; in spi_setup_slave()
473 fsl_dspi_cfg_speed(&dspi->priv, max_hz); in spi_setup_slave()
476 fsl_dspi_cfg_ctar_mode(&dspi->priv, cs, mode); in spi_setup_slave()
479 fsl_dspi_cfg_cs_active_state(&dspi->priv, cs, mode); in spi_setup_slave()
481 return &dspi->slave; in spi_setup_slave()
494 cpu_dspi_claim_bus(slave->bus, slave->cs); in spi_claim_bus()
496 fsl_dspi_clr_fifo(&dspi->priv); in spi_claim_bus()
498 /* check module TX and RX status */ in spi_claim_bus()
499 sr_val = dspi_read32(dspi->priv.flags, &dspi->priv.regs->sr); in spi_claim_bus()
501 debug("DSPI RX/TX not ready!\n"); in spi_claim_bus()
502 return -EIO; in spi_claim_bus()
512 dspi_halt(&dspi->priv, 1); in spi_release_bus()
513 cpu_dspi_release_bus(slave->bus.slave->cs); in spi_release_bus()
520 return dspi_xfer(&dspi->priv, slave->cs, bitlen, dout, din, flags); in spi_xfer()
526 struct fsl_dspi_priv *priv = dev_get_priv(dev->parent); in fsl_dspi_child_pre_probe()
528 if (slave_plat->cs >= priv->num_chipselect) { in fsl_dspi_child_pre_probe()
530 slave_plat->cs, priv->num_chipselect - 1); in fsl_dspi_child_pre_probe()
531 return -EINVAL; in fsl_dspi_child_pre_probe()
534 priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE; in fsl_dspi_child_pre_probe()
537 slave_plat->cs, slave_plat->max_hz, slave_plat->mode); in fsl_dspi_child_pre_probe()
549 dm_spi_bus = bus->uclass_priv; in fsl_dspi_probe()
555 priv->regs = (struct dspi *)plat->regs_addr; in fsl_dspi_probe()
556 priv->flags = plat->flags; in fsl_dspi_probe()
558 priv->bus_clk = gd->bus_clk; in fsl_dspi_probe()
560 priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK); in fsl_dspi_probe()
562 priv->num_chipselect = plat->num_chipselect; in fsl_dspi_probe()
563 priv->speed_hz = plat->speed_hz; in fsl_dspi_probe()
565 priv->charbit = 8; in fsl_dspi_probe()
567 dm_spi_bus->max_hz = plat->speed_hz; in fsl_dspi_probe()
574 debug("%s probe done, bus-num %d.\n", bus->name, bus->seq); in fsl_dspi_probe()
583 struct udevice *bus = dev->parent; in fsl_dspi_claim_bus()
590 cpu_dspi_claim_bus(bus->seq, slave_plat->cs); in fsl_dspi_claim_bus()
593 fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode); in fsl_dspi_claim_bus()
596 fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs, in fsl_dspi_claim_bus()
597 priv->mode); in fsl_dspi_claim_bus()
601 /* check module TX and RX status */ in fsl_dspi_claim_bus()
602 sr_val = dspi_read32(priv->flags, &priv->regs->sr); in fsl_dspi_claim_bus()
604 debug("DSPI RX/TX not ready!\n"); in fsl_dspi_claim_bus()
605 return -EIO; in fsl_dspi_claim_bus()
613 struct udevice *bus = dev->parent; in fsl_dspi_release_bus()
622 cpu_dspi_release_bus(bus->seq, slave_plat->cs); in fsl_dspi_release_bus()
632 debug("%s assigned req_seq %d.\n", bus->name, bus->req_seq); in fsl_dspi_bind()
639 struct fsl_dspi_platdata *plat = bus->platdata; in fsl_dspi_ofdata_to_platdata()
640 const void *blob = gd->fdt_blob; in fsl_dspi_ofdata_to_platdata()
643 if (fdtdec_get_bool(blob, node, "big-endian")) in fsl_dspi_ofdata_to_platdata()
644 plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG; in fsl_dspi_ofdata_to_platdata()
646 plat->num_chipselect = in fsl_dspi_ofdata_to_platdata()
647 fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT); in fsl_dspi_ofdata_to_platdata()
652 return -ENOMEM; in fsl_dspi_ofdata_to_platdata()
654 plat->regs_addr = addr; in fsl_dspi_ofdata_to_platdata()
656 plat->speed_hz = fdtdec_get_int(blob, in fsl_dspi_ofdata_to_platdata()
657 node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ); in fsl_dspi_ofdata_to_platdata()
659 debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n", in fsl_dspi_ofdata_to_platdata()
660 &plat->regs_addr, plat->speed_hz, in fsl_dspi_ofdata_to_platdata()
661 plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le", in fsl_dspi_ofdata_to_platdata()
662 plat->num_chipselect); in fsl_dspi_ofdata_to_platdata()
674 bus = dev->parent; in fsl_dspi_xfer()
677 return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags); in fsl_dspi_xfer()
694 * We store some chipselect special configure value in priv->ctar_val, in fsl_dspi_set_mode()
699 priv->mode = mode; in fsl_dspi_set_mode()
713 { .compatible = "fsl,vf610-dspi" },