376 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)  in cadence_qspi_apb_controller_init()  argument
380 	cadence_qspi_apb_controller_disable(plat->regbase);  in cadence_qspi_apb_controller_init()
383 	reg = readl(plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_controller_init()
387 	reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);  in cadence_qspi_apb_controller_init()
388 	reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);  in cadence_qspi_apb_controller_init()
389 	writel(reg, plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_controller_init()
392 	writel(0, plat->regbase + CQSPI_REG_REMAP);  in cadence_qspi_apb_controller_init()
395 	writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);  in cadence_qspi_apb_controller_init()
398 	writel(0, plat->regbase + CQSPI_REG_IRQMASK);  in cadence_qspi_apb_controller_init()
400 	cadence_qspi_apb_controller_enable(plat->regbase);  in cadence_qspi_apb_controller_init()
530 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,  in cadence_qspi_apb_indirect_read_setup()  argument
555 	writel(plat->trigger_address,  in cadence_qspi_apb_indirect_read_setup()
556 	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);  in cadence_qspi_apb_indirect_read_setup()
567 	writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);  in cadence_qspi_apb_indirect_read_setup()
577 		writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);  in cadence_qspi_apb_indirect_read_setup()
579 		writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);  in cadence_qspi_apb_indirect_read_setup()
592 	writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);  in cadence_qspi_apb_indirect_read_setup()
595 	reg = readl(plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_read_setup()
598 	writel(reg, plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_read_setup()
602 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)  in cadence_qspi_get_rd_sram_level()  argument
604 	u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);  in cadence_qspi_get_rd_sram_level()
609 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)  in cadence_qspi_wait_for_data()  argument
615 		reg = cadence_qspi_get_rd_sram_level(plat);  in cadence_qspi_wait_for_data()
624 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,  in cadence_qspi_apb_indirect_read_execute()  argument
631 	writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);  in cadence_qspi_apb_indirect_read_execute()
635 	       plat->regbase + CQSPI_REG_INDIRECTRD);  in cadence_qspi_apb_indirect_read_execute()
638 		ret = cadence_qspi_wait_for_data(plat);  in cadence_qspi_apb_indirect_read_execute()
647 			bytes_to_read *= plat->fifo_width;  in cadence_qspi_apb_indirect_read_execute()
655 				readsb(plat->ahbbase, rxbuf, bytes_to_read);  in cadence_qspi_apb_indirect_read_execute()
657 				readsl(plat->ahbbase, rxbuf,  in cadence_qspi_apb_indirect_read_execute()
661 			bytes_to_read = cadence_qspi_get_rd_sram_level(plat);  in cadence_qspi_apb_indirect_read_execute()
666 	ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,  in cadence_qspi_apb_indirect_read_execute()
675 	       plat->regbase + CQSPI_REG_INDIRECTRD);  in cadence_qspi_apb_indirect_read_execute()
682 	       plat->regbase + CQSPI_REG_INDIRECTRD);  in cadence_qspi_apb_indirect_read_execute()
687 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,  in cadence_qspi_apb_indirect_write_setup()  argument
699 	writel(plat->trigger_address,  in cadence_qspi_apb_indirect_write_setup()
700 	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);  in cadence_qspi_apb_indirect_write_setup()
704 	writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);  in cadence_qspi_apb_indirect_write_setup()
708 	writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);  in cadence_qspi_apb_indirect_write_setup()
710 	reg = readl(plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_write_setup()
713 	writel(reg, plat->regbase + CQSPI_REG_SIZE);  in cadence_qspi_apb_indirect_write_setup()
717 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,  in cadence_qspi_apb_indirect_write_execute()  argument
720 	unsigned int page_size = plat->page_size;  in cadence_qspi_apb_indirect_write_execute()
726 	writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);  in cadence_qspi_apb_indirect_write_execute()
730 	       plat->regbase + CQSPI_REG_INDIRECTWR);  in cadence_qspi_apb_indirect_write_execute()
736 			writesb(plat->ahbbase, txbuf, write_bytes);  in cadence_qspi_apb_indirect_write_execute()
738 			writesl(plat->ahbbase, txbuf, write_bytes >> 2);  in cadence_qspi_apb_indirect_write_execute()
740 		ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,  in cadence_qspi_apb_indirect_write_execute()
753 	ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,  in cadence_qspi_apb_indirect_write_execute()
762 	       plat->regbase + CQSPI_REG_INDIRECTWR);  in cadence_qspi_apb_indirect_write_execute()
768 	       plat->regbase + CQSPI_REG_INDIRECTWR);  in cadence_qspi_apb_indirect_write_execute()