90 	uint tx_slot;  member
171 	priv->tx_slot = 0;  in bcmstb_spi_probe()
208 	debug("WR ENDQP: %d\n", priv->tx_slot - 1);  in bcmstb_spi_submit()
209 	writel(priv->tx_slot - 1, &priv->regs->endqp);  in bcmstb_spi_submit()
212 		debug("WR CDRAM[%d]: %02x\n", priv->tx_slot - 1,  in bcmstb_spi_submit()
213 		      readl(&priv->regs->cdram[priv->tx_slot - 1]) & ~0x80);  in bcmstb_spi_submit()
214 		writel(readl(&priv->regs->cdram[priv->tx_slot - 1]) & ~0x80,  in bcmstb_spi_submit()
215 		       &priv->regs->cdram[priv->tx_slot - 1]);  in bcmstb_spi_submit()
304 		priv->tx_slot = 0;  in bcmstb_spi_xfer()
349 		priv->rx_slot = priv->tx_slot;  in bcmstb_spi_xfer()
351 		while (priv->tx_slot < NUM_CDRAM && tx_len > 0) {  in bcmstb_spi_xfer()
353 			debug("WR TXRAM[%d]: %02x\n", priv->tx_slot,  in bcmstb_spi_xfer()
356 			       &regs->txram[priv->tx_slot << 1]);  in bcmstb_spi_xfer()
357 			debug("WR CDRAM[%d]: %02x\n", priv->tx_slot, 0x8e);  in bcmstb_spi_xfer()
358 			writel(0x8e, &regs->cdram[priv->tx_slot]);  in bcmstb_spi_xfer()
359 			priv->tx_slot++;  in bcmstb_spi_xfer()
382 		priv->tx_slot %= NUM_CDRAM;  in bcmstb_spi_xfer()