Lines Matching +full:i2s +full:- +full:regs
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/i2s-regs.h>
14 #include <i2s.h>
22 #define TIMEOUT_I2S_TX 100 /* i2s transfer timeout */
25 * Sets the frame size for I2S LR clock
27 * @param i2s_reg i2s regiter address
32 unsigned int mod = readl(&i2s_reg->mod); in i2s_set_lr_framesize()
51 writel(mod, &i2s_reg->mod); in i2s_set_lr_framesize()
55 * Sets the i2s transfer control
57 * @param i2s_reg i2s regiter address
62 unsigned int con = readl(&i2s_reg->con); in i2s_txctrl()
63 unsigned int mod = readl(&i2s_reg->mod) & ~MOD_MASK; in i2s_txctrl()
73 writel(mod, &i2s_reg->mod); in i2s_txctrl()
74 writel(con, &i2s_reg->con); in i2s_txctrl()
80 * @param i2s_reg i2s regiter address
85 unsigned int mod = readl(&i2s_reg->mod); in i2s_set_bitclk_framesize()
105 writel(mod, &i2s_reg->mod); in i2s_set_bitclk_framesize()
111 * @param i2s_reg i2s regiter address
112 * @param flush Tx fifo flush command (0x00 - do not flush
113 * 0x80 - flush tx fifo)
118 setbits_le32(&i2s_reg->fic, flush); in i2s_fifo()
119 clrbits_le32(&i2s_reg->fic, flush); in i2s_fifo()
125 * @param i2s_reg i2s regiter address
128 * @return int value 0 for success, -1 in case of error
132 unsigned int mod = readl(&i2s_reg->mod); in i2s_set_sysclk_dir()
139 writel(mod, &i2s_reg->mod); in i2s_set_sysclk_dir()
145 * Sets I2S Clcok format
147 * @param fmt i2s clock properties
148 * @param i2s_reg i2s regiter address
150 * @return int value 0 for success, -1 in case of error
154 unsigned int mod = readl(&i2s_reg->mod); in i2s_set_fmt()
174 return -1; in i2s_set_fmt()
178 * INV flag is relative to the FORMAT flag - if set it simply in i2s_set_fmt()
193 return -1; in i2s_set_fmt()
204 debug("%s:set i2s clock direction failed\n", __func__); in i2s_set_fmt()
205 return -1; in i2s_set_fmt()
211 return -1; in i2s_set_fmt()
216 writel(mod, &i2s_reg->mod); in i2s_set_fmt()
225 * @param i2s_reg i2s regiter address
227 * @return int value 0 for success, -1 in case of error
231 unsigned int mod = readl(&i2s_reg->mod); in i2s_set_samplesize()
252 return -1; in i2s_set_samplesize()
254 writel(mod, &i2s_reg->mod); in i2s_set_samplesize()
265 (struct i2s_reg *)pi2s_tx->base_address; in i2s_transfer_tx_data()
269 return -1; /* invalid pcm data size */ in i2s_transfer_tx_data()
274 writel(*data++, &i2s_reg->txd); in i2s_transfer_tx_data()
276 data_size -= FIFO_LENGTH; in i2s_transfer_tx_data()
281 if (!(CON_TXFIFO_FULL & (readl(&i2s_reg->con)))) { in i2s_transfer_tx_data()
282 writel(*data++, &i2s_reg->txd); in i2s_transfer_tx_data()
283 data_size--; in i2s_transfer_tx_data()
287 debug("%s: I2S Transfer Timeout\n", __func__); in i2s_transfer_tx_data()
288 return -1; in i2s_transfer_tx_data()
301 (struct i2s_reg *)pi2s_tx->base_address; in i2s_tx_init()
302 if (pi2s_tx->id == 0) { in i2s_tx_init()
303 /* Initialize GPIO for I2S-0 */ in i2s_tx_init()
307 ret = set_epll_clk(pi2s_tx->samplingrate * pi2s_tx->rfs * 4); in i2s_tx_init()
308 } else if (pi2s_tx->id == 1) { in i2s_tx_init()
309 /* Initialize GPIO for I2S-1 */ in i2s_tx_init()
313 ret = set_epll_clk(pi2s_tx->audio_pll_clk); in i2s_tx_init()
315 debug("%s: unsupported i2s-%d bus\n", __func__, pi2s_tx->id); in i2s_tx_init()
316 return -1; in i2s_tx_init()
321 return -1; in i2s_tx_init()
325 ret = set_i2s_clk_source(pi2s_tx->id); in i2s_tx_init()
326 if (ret == -1) { in i2s_tx_init()
327 debug("%s: unsupported clock for i2s-%d\n", __func__, in i2s_tx_init()
328 pi2s_tx->id); in i2s_tx_init()
329 return -1; in i2s_tx_init()
332 if (pi2s_tx->id == 0) { in i2s_tx_init()
333 /*Reset the i2s module */ in i2s_tx_init()
334 writel(CON_RESET, &i2s_reg->con); in i2s_tx_init()
336 writel(MOD_OP_CLK | MOD_RCLKSRC, &i2s_reg->mod); in i2s_tx_init()
337 /* set i2s prescaler */ in i2s_tx_init()
338 writel(PSREN | PSVAL, &i2s_reg->psr); in i2s_tx_init()
341 ret = set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk, in i2s_tx_init()
342 (pi2s_tx->samplingrate * (pi2s_tx->rfs)), in i2s_tx_init()
343 pi2s_tx->id); in i2s_tx_init()
345 if (ret == -1) { in i2s_tx_init()
346 debug("%s: unsupported prescalar for i2s-%d\n", __func__, in i2s_tx_init()
347 pi2s_tx->id); in i2s_tx_init()
348 return -1; in i2s_tx_init()
351 /* Configure I2s format */ in i2s_tx_init()
355 i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs); in i2s_tx_init()
356 ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample); in i2s_tx_init()
359 return -1; in i2s_tx_init()
362 i2s_set_bitclk_framesize(i2s_reg, pi2s_tx->bfs); in i2s_tx_init()
363 /* disable i2s transfer flag and flush the fifo */ in i2s_tx_init()