Lines Matching +full:0 +full:x1b000000
14 #define SERDES_CMU_REGS(x) (0x0000 + (0x0c00 * (x)))
15 #define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x)))
16 #define SERDES_COMLANE_REGS 0x0a00
17 #define SERDES_WIZ_REGS 0x1fc0
19 #define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000)
20 #define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010)
21 #define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000)
22 #define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000)
23 #define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028)
24 #define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
25 #define SERDES_PLL_CTL_REG (SERDES_WIZ_REGS + 0x0034)
52 0xf000f0c0, /* SGMII */
53 0xf0e9f038, /* PCSR */
58 0xe0000000, /* SGMII */
59 0xee000000, /* PCSR */
71 {0x0000, 0x00800000, 0xffff0000},
72 {0x0014, 0x00008282, 0x0000ffff},
73 {0x0060, 0x00142438, 0x00ffffff},
74 {0x0064, 0x00c3c700, 0x00ffff00},
75 {0x0078, 0x0000c000, 0x0000ff00}
78 {0x0a00, 0x00000800, 0x0000ff00},
79 {0x0a08, 0x38a20000, 0xffff0000},
80 {0x0a30, 0x008a8a00, 0x00ffff00},
81 {0x0a84, 0x00000600, 0x0000ff00},
82 {0x0a94, 0x10000000, 0xff000000},
83 {0x0aa0, 0x81000000, 0xff000000},
84 {0x0abc, 0xff000000, 0xff000000},
85 {0x0ac0, 0x0000008b, 0x000000ff},
86 {0x0b08, 0x583f0000, 0xffff0000},
87 {0x0b0c, 0x0000004e, 0x000000ff}
90 {0x0004, 0x38000080, 0xff0000ff},
91 {0x0008, 0x00000000, 0x000000ff},
92 {0x000c, 0x02000000, 0xff000000},
93 {0x0010, 0x1b000000, 0xff000000},
94 {0x0014, 0x00006fb8, 0x0000ffff},
95 {0x0018, 0x758000e4, 0xffff00ff},
96 {0x00ac, 0x00004400, 0x0000ff00},
97 {0x002c, 0x00100800, 0x00ffff00},
98 {0x0080, 0x00820082, 0x00ff00ff},
99 {0x0084, 0x1d0f0385, 0xffffffff}
113 for (i = 0; i < size; i++) in ks2_serdes_cfg_setup()
122 for (i = 0; i < size; i++) in ks2_serdes_lane_config()
134 for (i = 0; i < num_lanes; i++) in ks2_serdes_init_cfg()
137 return 0; in ks2_serdes_init_cfg()
143 ks2_serdes_rmw(base + SERDES_CMU_REG_010(0), 0x0, SERDES_RESET); in ks2_serdes_cmu_comlane_enable()
145 ks2_serdes_rmw(base + SERDES_CMU_REG_010(1), 0x0, SERDES_RESET); in ks2_serdes_cmu_comlane_enable()
148 ks2_serdes_rmw(base + SERDES_CMU_REG_000(0), 0x03, 0x000000ff); in ks2_serdes_cmu_comlane_enable()
150 ks2_serdes_rmw(base + SERDES_CMU_REG_000(1), 0x03, 0x000000ff); in ks2_serdes_cmu_comlane_enable()
152 ks2_serdes_rmw(base + SERDES_COMLANE_REG_000, 0x5f, 0x000000ff); in ks2_serdes_cmu_comlane_enable()
165 0x1, SERDES_LANE_RESET); in ks2_serdes_lane_reset()
168 0x0, SERDES_LANE_RESET); in ks2_serdes_lane_reset()
175 ks2_serdes_lane_reset(base, 0, lane); in ks2_serdes_lane_enable()
184 0x1, SERDES_LANE_LOOPBACK); in ks2_serdes_lane_enable()
190 int ret = 0; in ks2_serdes_init()
192 for (i = 0; i < ARRAY_SIZE(cfgs); i++) in ks2_serdes_init()
204 for (i = 0; i < num_lanes; i++) in ks2_serdes_init()