4  * SPDX-License-Identifier:	GPL-2.0+
11 #include <asm/arch/imx-regs.h>
27 #define UCR1_TRDYEN	(1<<13) /* Transmitter ready interrupt enable */
29 #define UCR1_RRDYEN	(1<<9)	/* Recv ready interrupt enable */
30 #define UCR1_RDMAEN	(1<<8)	/* Recv ready DMA enable */
31 #define UCR1_IREN	(1<<7)	/* Infrared interface enable */
32 #define UCR1_TXMPTYEN	(1<<6)	/* Transimitter empty interrupt enable */
33 #define UCR1_RTSDEN	(1<<5)	/* RTS delta interrupt enable */
35 #define UCR1_TDMAEN	(1<<3)	/* Transmitter ready DMA enable */
39 #define UCR2_ESCI	(1<<15) /* Escape seq interrupt enable */
43 #define UCR2_ESCEN	(1<<11) /* Escape enable */
44 #define UCR2_PREN	(1<<8)  /* Parity enable */
48 #define UCR2_RTSEN	(1<<4)	/* Request to send interrupt enable */
52 #define UCR3_DTREN	(1<<13) /* DTR interrupt enable */
53 #define UCR3_PARERREN	(1<<12) /* Parity enable */
54 #define UCR3_FRAERREN	(1<<11) /* Frame error interrupt enable */
59 #define UCR3_RXDSEN	(1<<6)  /* Receive status interrupt enable */
60 #define UCR3_AIRINTEN	(1<<5)  /* Async IR wake interrupt enable */
61 #define UCR3_AWAKEN	(1<<4)  /* Async wake interrupt enable */
65 #define UCR3_BPEN	(1<<0)  /* Preset registers enable */
68 #define UCR4_ENIRI	(1<<8)  /* Serial infrared interrupt enable */
69 #define UCR4_WKEN	(1<<7)  /* Wake interrupt enable */
72 #define UCR4_TCEN	(1<<3)  /* Transmit complete interrupt enable */
73 #define UCR4_BKEN	(1<<2)  /* Break condition interrupt enable */
74 #define UCR4_OREN	(1<<1)  /* Receiver overrun interrupt enable */
75 #define UCR4_DREN	(1<<0)  /* Recv data ready interrupt enable */
142 static void _mxc_serial_init(struct mxc_uart *base)  in _mxc_serial_init()
144 	writel(0, &base->cr1);  in _mxc_serial_init()
145 	writel(0, &base->cr2);  in _mxc_serial_init()
147 	while (!(readl(&base->cr2) & UCR2_SRST));  in _mxc_serial_init()
149 	writel(0x704 | UCR3_ADNIMP, &base->cr3);  in _mxc_serial_init()
150 	writel(0x8000, &base->cr4);  in _mxc_serial_init()
151 	writel(0x2b, &base->esc);  in _mxc_serial_init()
152 	writel(0, &base->tim);  in _mxc_serial_init()
154 	writel(0, &base->ts);  in _mxc_serial_init()
157 static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,  in _mxc_serial_setbrg()
167 	writel(tmp, &base->fcr);  in _mxc_serial_setbrg()
169 	writel(0xf, &base->bir);  in _mxc_serial_setbrg()
170 	writel(clk / (2 * baudrate), &base->bmr);  in _mxc_serial_setbrg()
173 	       &base->cr2);  in _mxc_serial_setbrg()
174 	writel(UCR1_UARTEN, &base->cr1);  in _mxc_serial_setbrg()
185 static void mxc_serial_setbrg(void)  in mxc_serial_setbrg()
189 	if (!gd->baudrate)  in mxc_serial_setbrg()
190 		gd->baudrate = CONFIG_BAUDRATE;  in mxc_serial_setbrg()
192 	_mxc_serial_setbrg(mxc_base, clk, gd->baudrate, false);  in mxc_serial_setbrg()
195 static int mxc_serial_getc(void)  in mxc_serial_getc()
197 	while (readl(&mxc_base->ts) & UTS_RXEMPTY)  in mxc_serial_getc()
199 	return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */  in mxc_serial_getc()
202 static void mxc_serial_putc(const char c)  in mxc_serial_putc()
208 	writel(c, &mxc_base->txd);  in mxc_serial_putc()
211 	while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))  in mxc_serial_putc()
216 static int mxc_serial_tstc(void)  in mxc_serial_tstc()
219 	if (readl(&mxc_base->ts) & UTS_RXEMPTY)  in mxc_serial_tstc()
228 static int mxc_serial_init(void)  in mxc_serial_init()
237 static struct serial_device mxc_serial_drv = {
263 	struct mxc_serial_platdata *plat = dev->platdata;  in mxc_serial_setbrg()
266 	_mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);  in mxc_serial_setbrg()
271 static int mxc_serial_probe(struct udevice *dev)  in mxc_serial_probe()
273 	struct mxc_serial_platdata *plat = dev->platdata;  in mxc_serial_probe()
275 	_mxc_serial_init(plat->reg);  in mxc_serial_probe()
280 static int mxc_serial_getc(struct udevice *dev)  in mxc_serial_getc()
282 	struct mxc_serial_platdata *plat = dev->platdata;  in mxc_serial_getc()
283 	struct mxc_uart *const uart = plat->reg;  in mxc_serial_getc()
285 	if (readl(&uart->ts) & UTS_RXEMPTY)  in mxc_serial_getc()
286 		return -EAGAIN;  in mxc_serial_getc()
288 	return readl(&uart->rxd) & URXD_RX_DATA;  in mxc_serial_getc()
291 static int mxc_serial_putc(struct udevice *dev, const char ch)  in mxc_serial_putc()
293 	struct mxc_serial_platdata *plat = dev->platdata;  in mxc_serial_putc()
294 	struct mxc_uart *const uart = plat->reg;  in mxc_serial_putc()
296 	if (!(readl(&uart->ts) & UTS_TXEMPTY))  in mxc_serial_putc()
297 		return -EAGAIN;  in mxc_serial_putc()
299 	writel(ch, &uart->txd);  in mxc_serial_putc()
304 static int mxc_serial_pending(struct udevice *dev, bool input)  in mxc_serial_pending()
306 	struct mxc_serial_platdata *plat = dev->platdata;  in mxc_serial_pending()
307 	struct mxc_uart *const uart = plat->reg;  in mxc_serial_pending()
308 	uint32_t sr2 = readl(&uart->sr2);  in mxc_serial_pending()
316 static const struct dm_serial_ops mxc_serial_ops = {
324 static int mxc_serial_ofdata_to_platdata(struct udevice *dev)  in mxc_serial_ofdata_to_platdata()
326 	struct mxc_serial_platdata *plat = dev->platdata;  in mxc_serial_ofdata_to_platdata()
331 		return -EINVAL;  in mxc_serial_ofdata_to_platdata()
333 	plat->reg = (struct mxc_uart *)addr;  in mxc_serial_ofdata_to_platdata()
335 	plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),  in mxc_serial_ofdata_to_platdata()
336 					"fsl,dte-mode");  in mxc_serial_ofdata_to_platdata()
340 static const struct udevice_id mxc_serial_ids[] = {
341 	{ .compatible = "fsl,imx6ul-uart" },
342 	{ .compatible = "fsl,imx7d-uart" },
364 static inline void _debug_uart_init(void)  in _debug_uart_init()
373 static inline void _debug_uart_putc(int ch)  in _debug_uart_putc()
377 	while (!(readl(&base->ts) & UTS_TXEMPTY))  in _debug_uart_putc()
380 	writel(ch, &base->txd);  in _debug_uart_putc()