140 	union FL_CTL_T fl_reg;  in nandc_bch_sel()  local
143 	fl_reg.d32 = 0;  in nandc_bch_sel()
144 	fl_reg.V6.rst = 1;  in nandc_bch_sel()
147 		nandc_writel(fl_reg.d32, NANDC_V9_FLCTL);  in nandc_bch_sel()
161 		nandc_writel(fl_reg.d32, NANDC_FLCTL);  in nandc_bch_sel()
192 	union FL_CTL_T fl_reg;  in nandc_xfer_start()  local
198 	fl_reg.d32 = 0;  in nandc_xfer_start()
200 		fl_reg.V9.flash_rdn = dir;  in nandc_xfer_start()
201 		fl_reg.V9.bypass = 1;  in nandc_xfer_start()
202 		fl_reg.V9.tr_count = 1;  in nandc_xfer_start()
203 		fl_reg.V9.async_tog_mix = 1;  in nandc_xfer_start()
204 		fl_reg.V9.cor_able = 1;  in nandc_xfer_start()
205 		fl_reg.V9.st_addr = 0;  in nandc_xfer_start()
206 		fl_reg.V9.page_num = (n_sec + 1) / 2;  in nandc_xfer_start()
208 		fl_reg.V9.flash_st_mod = 1;  in nandc_xfer_start()
234 					fl_reg.V6.page_num * 1024);  in nandc_xfer_start()
238 					fl_reg.V6.page_num * 128);  in nandc_xfer_start()
253 		nandc_writel(fl_reg.d32, NANDC_V9_FLCTL);  in nandc_xfer_start()
254 		fl_reg.V9.flash_st = 1;  in nandc_xfer_start()
255 		nandc_writel(fl_reg.d32, NANDC_V9_FLCTL);  in nandc_xfer_start()
262 		fl_reg.V6.rdn = dir;  in nandc_xfer_start()
263 		fl_reg.V6.dma = 1;  in nandc_xfer_start()
264 		fl_reg.V6.tr_count = 1;  in nandc_xfer_start()
265 		fl_reg.V6.async_tog_mix = 1;  in nandc_xfer_start()
266 		fl_reg.V6.cor_en = 1;  in nandc_xfer_start()
267 		fl_reg.V6.st_addr = 0;  in nandc_xfer_start()
286 		fl_reg.V6.page_num = (n_sec + 1) / 2;  in nandc_xfer_start()
297 					fl_reg.V6.page_num * 1024);  in nandc_xfer_start()
301 					fl_reg.V6.page_num * 128);  in nandc_xfer_start()
315 		nandc_writel(fl_reg.d32, NANDC_FLCTL);  in nandc_xfer_start()
316 		fl_reg.V6.start = 1;  in nandc_xfer_start()
317 		nandc_writel(fl_reg.d32, NANDC_FLCTL);  in nandc_xfer_start()
326 	union FL_CTL_T fl_reg;  in nandc_xfer_done()  local
335 				fl_reg.d32 = nandc_readl(NANDC_V9_FLCTL);  in nandc_xfer_done()
338 			} while (stat_reg.V9.mtrans_cnt < fl_reg.V9.page_num ||  in nandc_xfer_done()
339 				 fl_reg.V9.tr_rdy == 0);  in nandc_xfer_done()
343 				fl_reg.d32 = nandc_readl(NANDC_V9_FLCTL);  in nandc_xfer_done()
345 			} while (fl_reg.V9.tr_rdy == 0);  in nandc_xfer_done()
354 				fl_reg.d32 = nandc_readl(NANDC_FLCTL);  in nandc_xfer_done()
357 			} while (stat_reg.V6.mtrans_cnt < fl_reg.V6.page_num ||  in nandc_xfer_done()
358 				 fl_reg.V6.tr_rdy == 0);  in nandc_xfer_done()
361 				fl_reg.d32 = nandc_readl(NANDC_FLCTL);  in nandc_xfer_done()
363 			} while (fl_reg.V6.tr_rdy == 0);  in nandc_xfer_done()
367 				fl_reg.d32 = nandc_readl(NANDC_FLCTL);  in nandc_xfer_done()
368 			} while ((fl_reg.V6.tr_rdy == 0));  in nandc_xfer_done()