46 		ctl_reg.V9.wp = 1;  in nandc_init()
47 		ctl_reg.V9.sif_read_delay = 2;  in nandc_init()
157 		tmp.V9.bchmode = bch_config;  in nandc_bch_sel()
158 		tmp.V9.bchrst = 1;  in nandc_bch_sel()
200 		fl_reg.V9.flash_rdn = dir;  in nandc_xfer_start()
201 		fl_reg.V9.bypass = 1;  in nandc_xfer_start()
202 		fl_reg.V9.tr_count = 1;  in nandc_xfer_start()
203 		fl_reg.V9.async_tog_mix = 1;  in nandc_xfer_start()
204 		fl_reg.V9.cor_able = 1;  in nandc_xfer_start()
205 		fl_reg.V9.st_addr = 0;  in nandc_xfer_start()
206 		fl_reg.V9.page_num = (n_sec + 1) / 2;  in nandc_xfer_start()
208 		fl_reg.V9.flash_st_mod = 1;  in nandc_xfer_start()
244 		master_reg.V9.incr_num = 16;  in nandc_xfer_start()
245 		master_reg.V9.burst = 7;  in nandc_xfer_start()
246 		master_reg.V9.hsize = 2;  in nandc_xfer_start()
247 		master_reg.V9.bus_mode = 1;  in nandc_xfer_start()
248 		master_reg.V9.ahb_wr = !dir;  in nandc_xfer_start()
249 		master_reg.V9.ahb_wr_st = 1;  in nandc_xfer_start()
250 		master_reg.V9.redundance_size = 0;  in nandc_xfer_start()
254 		fl_reg.V9.flash_st = 1;  in nandc_xfer_start()
333 		if (master_reg.V9.ahb_wr != 0) {  in nandc_xfer_done()
338 			} while (stat_reg.V9.mtrans_cnt < fl_reg.V9.page_num ||  in nandc_xfer_done()
339 				 fl_reg.V9.tr_rdy == 0);  in nandc_xfer_done()
345 			} while (fl_reg.V9.tr_rdy == 0);  in nandc_xfer_done()
392 					if (bch_st_reg.V9.fail0 || bch_st_reg.V9.fail1) {  in nandc_xfer_data()
395 						u32 tmp = max((u32)bch_st_reg.V9.err_bits0,  in nandc_xfer_data()
396 							      (u32)bch_st_reg.V9.err_bits1);  in nandc_xfer_data()
400 					if (bch_st_reg.V9.fail0)  in nandc_xfer_data()
403 						status = bch_st_reg.V9.err_bits0;  in nandc_xfer_data()