52 		ctl_reg.V6.wp = 1;  in nandc_init()
74 	tmp.V6.cs = 0x01 << chip_sel;  in nandc_flash_cs()
83 	tmp.V6.cs = 0;  in nandc_flash_de_cs()
84 	tmp.V6.flash_abort_clear = 0;  in nandc_flash_de_cs()
104 		if (tmp.V6.rdy != 0)  in nandc_wait_flash_ready()
144 	fl_reg.V6.rst = 1;  in nandc_bch_sel()
163 		tmp.V6.addr = 0x10;  in nandc_bch_sel()
164 		tmp.V6.bch_mode1 = 0;  in nandc_bch_sel()
166 			tmp.V6.bch_mode = 0;  in nandc_bch_sel()
168 			tmp.V6.bch_mode = 1;  in nandc_bch_sel()
170 			tmp.V6.bch_mode1 = 1;  in nandc_bch_sel()
171 			tmp.V6.bch_mode = 1;  in nandc_bch_sel()
173 				tmp.V6.bch_mode = 0;  in nandc_bch_sel()
175 		tmp.V6.rst = 1;  in nandc_bch_sel()
234 					fl_reg.V6.page_num * 1024);  in nandc_xfer_start()
238 					fl_reg.V6.page_num * 128);  in nandc_xfer_start()
258 		bch_reg.V6.addr = 0x10;  in nandc_xfer_start()
259 		bch_reg.V6.power_down = 0;  in nandc_xfer_start()
260 		bch_reg.V6.region = 0;  in nandc_xfer_start()
262 		fl_reg.V6.rdn = dir;  in nandc_xfer_start()
263 		fl_reg.V6.dma = 1;  in nandc_xfer_start()
264 		fl_reg.V6.tr_count = 1;  in nandc_xfer_start()
265 		fl_reg.V6.async_tog_mix = 1;  in nandc_xfer_start()
266 		fl_reg.V6.cor_en = 1;  in nandc_xfer_start()
267 		fl_reg.V6.st_addr = 0;  in nandc_xfer_start()
270 		master_reg.V6.bus_mode = 0;  in nandc_xfer_start()
286 		fl_reg.V6.page_num = (n_sec + 1) / 2;  in nandc_xfer_start()
297 					fl_reg.V6.page_num * 1024);  in nandc_xfer_start()
301 					fl_reg.V6.page_num * 128);  in nandc_xfer_start()
306 		master_reg.V6.incr_num = 16;  in nandc_xfer_start()
307 		master_reg.V6.burst = 7;  in nandc_xfer_start()
308 		master_reg.V6.hsize = 2;  in nandc_xfer_start()
309 		master_reg.V6.bus_mode = 1;  in nandc_xfer_start()
310 		master_reg.V6.ahb_wr = !dir;  in nandc_xfer_start()
311 		master_reg.V6.ahb_wr_st = 1;  in nandc_xfer_start()
316 		fl_reg.V6.start = 1;  in nandc_xfer_start()
349 		if (master_reg.V6.bus_mode != 0) {  in nandc_xfer_done()
352 		if (master_reg.V6.ahb_wr != 0) {  in nandc_xfer_done()
357 			} while (stat_reg.V6.mtrans_cnt < fl_reg.V6.page_num ||  in nandc_xfer_done()
358 				 fl_reg.V6.tr_rdy == 0);  in nandc_xfer_done()
363 			} while (fl_reg.V6.tr_rdy == 0);  in nandc_xfer_done()
368 			} while ((fl_reg.V6.tr_rdy == 0));  in nandc_xfer_done()
413 				if (bch_st_reg.V6.fail0 || bch_st_reg.V6.fail1) {  in nandc_xfer_data()
419 					max(bch_st_reg.V6.err_bits0 |  in nandc_xfer_data()
420 					    ((u32)bch_st_reg.V6.err_bits0_5 << 5),  in nandc_xfer_data()
421 					    bch_st_reg.V6.err_bits1 |  in nandc_xfer_data()
422 					    ((u32)bch_st_reg.V6.err_bits1_5 << 5));  in nandc_xfer_data()