Lines Matching +full:timing +full:-
5 * SPDX-License-Identifier: GPL-2.0+
19 u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */
21 u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */
23 u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */
25 u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */
31 u32 pmem; /* Common memory space timing register */
32 u32 patt; /* Attribute memory space timing registers */
38 u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */
40 u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */
42 u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */
44 u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */
50 u32 sdtr1; /* SDRAM Timing register 1 */
51 u32 sdtr2; /* SDRAM Timing register 2 */
53 u32 sdrtr; /* SDRAM Refresh timing register */
76 #define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
77 #define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
81 #define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
102 while (regs->sdsr & FMC_SDSR_BUSY) \
159 struct stm32_sdram_timing *timing; in stm32_sdram_init() local
160 struct stm32_fmc_regs *regs = params->base; in stm32_sdram_init()
167 if (params->family == STM32H7_FMC) in stm32_sdram_init()
168 clrbits_le32(®s->bcr1, FMC_BCR1_FMCEN); in stm32_sdram_init()
170 for (i = 0; i < params->no_sdram_banks; i++) { in stm32_sdram_init()
171 control = params->bank_params[i].sdram_control; in stm32_sdram_init()
172 timing = params->bank_params[i].sdram_timing; in stm32_sdram_init()
173 target_bank = params->bank_params[i].target_bank; in stm32_sdram_init()
174 ref_count = params->bank_params[i].sdram_ref_count; in stm32_sdram_init()
176 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT in stm32_sdram_init()
177 | control->cas_latency << FMC_SDCR_CAS_SHIFT in stm32_sdram_init()
178 | control->no_banks << FMC_SDCR_NB_SHIFT in stm32_sdram_init()
179 | control->memory_width << FMC_SDCR_MWID_SHIFT in stm32_sdram_init()
180 | control->no_rows << FMC_SDCR_NR_SHIFT in stm32_sdram_init()
181 | control->no_columns << FMC_SDCR_NC_SHIFT in stm32_sdram_init()
182 | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT in stm32_sdram_init()
183 | control->rd_burst << FMC_SDCR_RBURST_SHIFT, in stm32_sdram_init()
184 ®s->sdcr1); in stm32_sdram_init()
187 writel(control->cas_latency << FMC_SDCR_CAS_SHIFT in stm32_sdram_init()
188 | control->no_banks << FMC_SDCR_NB_SHIFT in stm32_sdram_init()
189 | control->memory_width << FMC_SDCR_MWID_SHIFT in stm32_sdram_init()
190 | control->no_rows << FMC_SDCR_NR_SHIFT in stm32_sdram_init()
191 | control->no_columns << FMC_SDCR_NC_SHIFT, in stm32_sdram_init()
192 ®s->sdcr2); in stm32_sdram_init()
194 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT in stm32_sdram_init()
195 | timing->trp << FMC_SDTR_TRP_SHIFT in stm32_sdram_init()
196 | timing->twr << FMC_SDTR_TWR_SHIFT in stm32_sdram_init()
197 | timing->trc << FMC_SDTR_TRC_SHIFT in stm32_sdram_init()
198 | timing->tras << FMC_SDTR_TRAS_SHIFT in stm32_sdram_init()
199 | timing->txsr << FMC_SDTR_TXSR_SHIFT in stm32_sdram_init()
200 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, in stm32_sdram_init()
201 ®s->sdtr1); in stm32_sdram_init()
204 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT in stm32_sdram_init()
205 | timing->trp << FMC_SDTR_TRP_SHIFT in stm32_sdram_init()
206 | timing->twr << FMC_SDTR_TWR_SHIFT in stm32_sdram_init()
207 | timing->trc << FMC_SDTR_TRC_SHIFT in stm32_sdram_init()
208 | timing->tras << FMC_SDTR_TRAS_SHIFT in stm32_sdram_init()
209 | timing->txsr << FMC_SDTR_TXSR_SHIFT in stm32_sdram_init()
210 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, in stm32_sdram_init()
211 ®s->sdtr2); in stm32_sdram_init()
218 writel(ctb | FMC_SDCMR_MODE_START_CLOCK, ®s->sdcmr); in stm32_sdram_init()
219 udelay(200); /* 200 us delay, page 10, "Power-Up" */ in stm32_sdram_init()
222 writel(ctb | FMC_SDCMR_MODE_PRECHARGE, ®s->sdcmr); in stm32_sdram_init()
227 ®s->sdcmr); in stm32_sdram_init()
232 | control->cas_latency << SDRAM_MODE_CAS_SHIFT) in stm32_sdram_init()
234 ®s->sdcmr); in stm32_sdram_init()
238 writel(ctb | FMC_SDCMR_MODE_NORMAL, ®s->sdcmr); in stm32_sdram_init()
242 writel(ref_count << 1, ®s->sdrtr); in stm32_sdram_init()
246 if (params->family == STM32H7_FMC) in stm32_sdram_init()
247 setbits_le32(®s->bcr1, FMC_BCR1_FMCEN); in stm32_sdram_init()
266 return -EINVAL; in stm32_fmc_ofdata_to_platdata()
269 bank_params = ¶ms->bank_params[bank]; in stm32_fmc_ofdata_to_platdata()
271 (long unsigned int *)&bank_params->target_bank); in stm32_fmc_ofdata_to_platdata()
273 if (bank_params->target_bank >= MAX_SDRAM_BANK) { in stm32_fmc_ofdata_to_platdata()
275 bank_params->target_bank); in stm32_fmc_ofdata_to_platdata()
276 return -EINVAL; in stm32_fmc_ofdata_to_platdata()
279 debug("Find bank %s %u\n", bank_name, bank_params->target_bank); in stm32_fmc_ofdata_to_platdata()
281 params->bank_params[bank].sdram_control = in stm32_fmc_ofdata_to_platdata()
284 "st,sdram-control", in stm32_fmc_ofdata_to_platdata()
287 if (!params->bank_params[bank].sdram_control) { in stm32_fmc_ofdata_to_platdata()
288 pr_err("st,sdram-control not found for %s", in stm32_fmc_ofdata_to_platdata()
290 return -EINVAL; in stm32_fmc_ofdata_to_platdata()
294 params->bank_params[bank].sdram_timing = in stm32_fmc_ofdata_to_platdata()
297 "st,sdram-timing", in stm32_fmc_ofdata_to_platdata()
300 if (!params->bank_params[bank].sdram_timing) { in stm32_fmc_ofdata_to_platdata()
301 pr_err("st,sdram-timing not found for %s", in stm32_fmc_ofdata_to_platdata()
303 return -EINVAL; in stm32_fmc_ofdata_to_platdata()
307 bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node, in stm32_fmc_ofdata_to_platdata()
308 "st,sdram-refcount", 8196); in stm32_fmc_ofdata_to_platdata()
312 params->no_sdram_banks = bank; in stm32_fmc_ofdata_to_platdata()
313 debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); in stm32_fmc_ofdata_to_platdata()
326 return -EINVAL; in stm32_fmc_probe()
328 params->base = (struct stm32_fmc_regs *)addr; in stm32_fmc_probe()
329 params->family = dev_get_driver_data(dev); in stm32_fmc_probe()
362 { .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
363 { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },