19 	u32 btr1;	/* SRAM/NOR-Flash Chip select timing register 1 */
21 	u32 btr2;	/* SRAM/NOR-Flash Chip select timing register 2 */
23 	u32 btr3;	/* SRAM/NOR-Flash Chip select timing register 3 */
25 	u32 btr4;	/* SRAM/NOR-Flash Chip select timing register 4 */
31 	u32 pmem;	/* Common memory space timing register */
32 	u32 patt;	/* Attribute memory space timing registers  */
38 	u32 bwtr1;	/* SRAM/NOR-Flash write timing register 1 */
40 	u32 bwtr2;	/* SRAM/NOR-Flash write timing register 2 */
42 	u32 bwtr3;	/* SRAM/NOR-Flash write timing register 3 */
44 	u32 bwtr4;	/* SRAM/NOR-Flash write timing register 4 */
50 	u32 sdtr1;	/* SDRAM Timing register 1 */
51 	u32 sdtr2;	/* SDRAM Timing register 2 */
53 	u32 sdrtr;	/* SDRAM Refresh timing register */
159 	struct stm32_sdram_timing *timing;  in stm32_sdram_init()  local
172 		timing = params->bank_params[i].sdram_timing;  in stm32_sdram_init()
194 		writel(timing->trcd << FMC_SDTR_TRCD_SHIFT  in stm32_sdram_init()
195 			| timing->trp << FMC_SDTR_TRP_SHIFT  in stm32_sdram_init()
196 			| timing->twr << FMC_SDTR_TWR_SHIFT  in stm32_sdram_init()
197 			| timing->trc << FMC_SDTR_TRC_SHIFT  in stm32_sdram_init()
198 			| timing->tras << FMC_SDTR_TRAS_SHIFT  in stm32_sdram_init()
199 			| timing->txsr << FMC_SDTR_TXSR_SHIFT  in stm32_sdram_init()
200 			| timing->tmrd << FMC_SDTR_TMRD_SHIFT,  in stm32_sdram_init()
204 			writel(timing->trcd << FMC_SDTR_TRCD_SHIFT  in stm32_sdram_init()
205 				| timing->trp << FMC_SDTR_TRP_SHIFT  in stm32_sdram_init()
206 				| timing->twr << FMC_SDTR_TWR_SHIFT  in stm32_sdram_init()
207 				| timing->trc << FMC_SDTR_TRC_SHIFT  in stm32_sdram_init()
208 				| timing->tras << FMC_SDTR_TRAS_SHIFT  in stm32_sdram_init()
209 				| timing->txsr << FMC_SDTR_TXSR_SHIFT  in stm32_sdram_init()
210 				| timing->tmrd << FMC_SDTR_TMRD_SHIFT,  in stm32_sdram_init()
297 						  "st,sdram-timing",  in stm32_fmc_ofdata_to_platdata()
301 			pr_err("st,sdram-timing not found for %s",  in stm32_fmc_ofdata_to_platdata()