895 	u32 mr1_mr3, mr11, mr22, vref_out, vref_inner;  in set_ds_odt()  local
1009 			vref_inner = 0x80;  in set_ds_odt()
1011 			vref_inner = (2 * dram_drv_ohm + phy_odt_ohm) * 128 /  in set_ds_odt()
1014 			vref_inner = phy_odt_ohm * 128 /  in set_ds_odt()
1025 			vref_inner =  in set_ds_odt()
1029 			vref_inner =  in set_ds_odt()
1063 		writel(vref_inner, PHY_REG(phy_base, 0x118 + i * 0x10));  in set_ds_odt()
1701 	u32 vref_inner;  in data_training_rd()  local
1707 	vref_inner = readl(PHY_REG(phy_base, 0x128)) & 0xff;  in data_training_rd()
1708 	if (dramtype == DDR3 && vref_inner == 0x80) {  in data_training_rd()
1710 			writel(vref_inner - 0xa,  in data_training_rd()
1795 	if (dramtype == DDR3 && vref_inner == 0x80) {  in data_training_rd()
1797 			writel(vref_inner,  in data_training_rd()
3095 	p_fsp_param->vref_inner = readl(PHY_REG(phy_base, 0x128));  in save_fsp_param()