Lines Matching refs:pctl_base
497 void __iomem *pctl_base = dram->pctl; in sw_set_req() local
500 writel(PCTL2_SW_DONE_CLEAR, pctl_base + DDR_PCTL2_SWCTL); in sw_set_req()
505 void __iomem *pctl_base = dram->pctl; in sw_set_ack() local
508 writel(PCTL2_SW_DONE, pctl_base + DDR_PCTL2_SWCTL); in sw_set_ack()
511 if (readl(pctl_base + DDR_PCTL2_SWSTAT) & in sw_set_ack()
521 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map() local
540 sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0), in set_ctl_address_map()
545 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6 + in set_ctl_address_map()
550 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31); in set_ctl_address_map()
552 setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8); in set_ctl_address_map()
555 clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f); in set_ctl_address_map()
809 void __iomem *pctl_base = dram->pctl; in set_lp4_vref() local
865 clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in set_lp4_vref()
870 clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in set_lp4_vref()
881 void __iomem *pctl_base = dram->pctl; in set_ds_odt() local
1087 mr1_mr3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in set_ds_odt()
1091 mr1_mr3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in set_ds_odt()
1159 mr11 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in set_ds_odt()
1171 clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in set_ds_odt()
1178 mr22 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in set_ds_odt()
1194 clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in set_ds_odt()
1203 clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in set_ds_odt()
1210 clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in set_ds_odt()
1296 void __iomem *pctl_base = dram->pctl; in update_refresh_reg() local
1299 ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1); in update_refresh_reg()
1300 writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3); in update_refresh_reg()
1313 void __iomem *pctl_base = dram->pctl; in read_mr() local
1321 pctl_read_mr(pctl_base, rank, mr_num); in read_mr()
1338 void __iomem *pctl_base = dram->pctl; in send_a_refresh() local
1340 while (readl(pctl_base + DDR_PCTL2_DBGSTAT) & 0x3) in send_a_refresh()
1342 writel(0x3, pctl_base + DDR_PCTL2_DBGCMD); in send_a_refresh()
1347 void __iomem *pctl_base = dram->pctl; in enter_sr() local
1350 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, PCTL2_SELFREF_SW); in enter_sr()
1352 if (((readl(pctl_base + DDR_PCTL2_STAT) & in enter_sr()
1355 ((readl(pctl_base + DDR_PCTL2_STAT) & in enter_sr()
1361 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, PCTL2_SELFREF_SW); in enter_sr()
1362 while ((readl(pctl_base + DDR_PCTL2_STAT) & in enter_sr()
1511 void __iomem *pctl_base = dram->pctl; in low_power_update() local
1515 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, en & 0xf); in low_power_update()
1517 lp_stat = readl(pctl_base + DDR_PCTL2_PWRCTL) & 0xf; in low_power_update()
1518 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 0xf); in low_power_update()
1624 void __iomem *pctl_base = dram->pctl; in data_training_wl() local
1635 cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3; in data_training_wl()
1636 tmp = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + DDR_PCTL2_INIT3) & in data_training_wl()
1694 void __iomem *pctl_base = dram->pctl; in data_training_rd() local
1727 cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3; in data_training_rd()
1729 trefi_1x = ((readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + in data_training_rd()
1731 trfc_1x = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + in data_training_rd()
1811 void __iomem *pctl_base = dram->pctl; in data_training_wr() local
1847 cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3; in data_training_wr()
1848 trefi_1x = ((readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + in data_training_wr()
1850 trfc_1x = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + in data_training_wr()
1912 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + in data_training_wr()
2204 void __iomem *pctl_base = dram->pctl; in update_noc_timing() local
2208 bl = ((readl(pctl_base + DDR_PCTL2_MSTR) >> 16) & 0xf) * 2; in update_noc_timing()
2309 void __iomem *pctl_base = dram->pctl; in dram_all_config() local
2325 cs_pst = (readl(pctl_base + DDR_PCTL2_ADDRMAP0) & 0x1f) + in dram_all_config()
2340 void __iomem *pctl_base = dram->pctl; in enable_low_power() local
2358 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); in enable_low_power()
2360 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); in enable_low_power()
2362 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); in enable_low_power()
2364 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); in enable_low_power()
2365 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3)); in enable_low_power()
2373 void __iomem *pctl_base = dram->pctl; in ddr_set_atags() local
2409 cs_pst = (readl(pctl_base + DDR_PCTL2_ADDRMAP0) & 0x1f) + in ddr_set_atags()
2498 void __iomem *pctl_base = dram->pctl; in sdram_init_() local
2521 setbits_le32(pctl_base + DDR_PCTL2_SCHED, 1 << 2); in sdram_init_()
2523 clrsetbits_le32(pctl_base + DDR_PCTL2_SCHED1, 0xff, 0x1 << 0); in sdram_init_()
2525 clrbits_le32(pctl_base + DDR_PCTL2_SCHED, 1 << 2); in sdram_init_()
2531 tmp = readl(pctl_base + DDR_PCTL2_RFSHTMG); in sdram_init_()
2534 pctl_base + DDR_PCTL2_RFSHTMG); in sdram_init_()
2538 setbits_le32(pctl_base + DDR_PCTL2_MSTR, 0x1 << 29); in sdram_init_()
2540 clrsetbits_le32(pctl_base + DDR_PCTL2_MSTR2, 0x3, 0); in sdram_init_()
2546 setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4)); in sdram_init_()
2550 while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0) { in sdram_init_()
2563 mr_tmp = readl(pctl_base + DDR_PCTL2_INIT6); in sdram_init_()
2573 mr_tmp = readl(pctl_base + DDR_PCTL2_INIT7); in sdram_init_()
2607 mr_tmp = readl(pctl_base + DDR_PCTL2_INIT7); in sdram_init_()
2638 void __iomem *pctl_base = dram->pctl; in dram_detect_cap() local
2709 pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL); in dram_detect_cap()
2710 writel(0, pctl_base + DDR_PCTL2_PWRCTL); in dram_detect_cap()
2742 writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL); in dram_detect_cap()
2766 void __iomem *pctl_base = dram->pctl; in dram_detect_cs1_row() local
2777 cs_pst = (readl(pctl_base + DDR_PCTL2_ADDRMAP0) & 0x1f) + in dram_detect_cs1_row()
2941 void __iomem *pctl_base = dram->pctl; in pre_set_rate() local
2955 pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in pre_set_rate()
2966 tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_RFSHTMG); in pre_set_rate()
2969 pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_RFSHTMG); in pre_set_rate()
2996 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in pre_set_rate()
3015 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in pre_set_rate()
3030 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in pre_set_rate()
3043 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in pre_set_rate()
3065 void __iomem *pctl_base = dram->pctl; in save_fsp_param() local
3099 temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in save_fsp_param()
3106 temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in save_fsp_param()
3113 temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in save_fsp_param()
3122 temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in save_fsp_param()
3127 temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in save_fsp_param()
3316 void __iomem *pctl_base = dram->pctl; in ddr_set_rate() local
3329 while ((readl(pctl_base + DDR_PCTL2_STAT) & in ddr_set_rate()
3335 dst_init3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in ddr_set_rate()
3341 cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3; in ddr_set_rate()
3342 cur_init3 = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + in ddr_set_rate()
3358 setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, in ddr_set_rate()
3368 clrbits_le32(pctl_base + DDR_PCTL2_DFIMISC, in ddr_set_rate()
3374 setbits_le32(pctl_base + DDR_PCTL2_MSTR, PCTL2_DLL_OFF_MODE); in ddr_set_rate()
3376 clrbits_le32(pctl_base + DDR_PCTL2_MSTR, PCTL2_DLL_OFF_MODE); in ddr_set_rate()
3378 setbits_le32(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + DDR_PCTL2_ZQCTL0, in ddr_set_rate()
3380 setbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_ZQCTL0, in ddr_set_rate()
3406 while ((readl(pctl_base + DDR_PCTL2_DFISTAT) & in ddr_set_rate()
3417 setbits_le32(pctl_base + DDR_PCTL2_MSTR, 0x1 << 29); in ddr_set_rate()
3418 clrsetbits_le32(pctl_base + DDR_PCTL2_MSTR2, 0x3, dst_fsp); in ddr_set_rate()
3428 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_INIT4); in ddr_set_rate()
3461 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in ddr_set_rate()
3472 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + in ddr_set_rate()
3485 clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, in ddr_set_rate()