1817 	u32 mr_tmp, cl, cwl, phy_fsp, offset = 0;  in data_training_wr()  local
1912 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) +  in data_training_wr()
1914 		pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK,  in data_training_wr()
2501 	u32 mr_tmp, tmp;  in sdram_init_()  local
2563 		mr_tmp = readl(pctl_base + DDR_PCTL2_INIT6);  in sdram_init_()
2566 			      mr_tmp >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK,  in sdram_init_()
2570 			      mr_tmp >> PCTL2_LPDDR4_MR12_SHIFT & PCTL2_MR_MASK,  in sdram_init_()
2573 		mr_tmp = readl(pctl_base + DDR_PCTL2_INIT7);  in sdram_init_()
2576 			      mr_tmp >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK,  in sdram_init_()
2599 		mr_tmp = read_mr(dram, 1, 14, LPDDR4);  in sdram_init_()
2601 		if (mr_tmp != 0x4d)  in sdram_init_()
2607 		mr_tmp = readl(pctl_base + DDR_PCTL2_INIT7);  in sdram_init_()
2610 			      mr_tmp >> PCTL2_LPDDR4_MR14_SHIFT & PCTL2_MR_MASK,  in sdram_init_()
2944 	u32 mr_tmp;  in pre_set_rate()  local
2996 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3000 			      ((mr_tmp >> PCTL2_LPDDR4_MR13_SHIFT &  in pre_set_rate()
3003 		writel(((mr_tmp >> PCTL2_LPDDR4_MR13_SHIFT &  in pre_set_rate()
3009 			      mr_tmp >> PCTL2_LPDDR234_MR3_SHIFT &  in pre_set_rate()
3012 		writel(mr_tmp >> PCTL2_LPDDR234_MR3_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3015 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3019 			      mr_tmp >> PCTL2_LPDDR234_MR1_SHIFT &  in pre_set_rate()
3022 		writel(mr_tmp >> PCTL2_LPDDR234_MR1_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3025 		pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK,  in pre_set_rate()
3027 		writel(mr_tmp & PCTL2_MR_MASK,  in pre_set_rate()
3030 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3034 			      mr_tmp >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3036 		writel(mr_tmp >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3040 			      mr_tmp >> PCTL2_LPDDR4_MR12_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3043 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3047 			      mr_tmp >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3049 		writel(mr_tmp >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3053 			      mr_tmp >> PCTL2_LPDDR4_MR14_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3055 		writel(mr_tmp >> PCTL2_LPDDR4_MR14_SHIFT & PCTL2_MR_MASK,  in pre_set_rate()
3312 	u32 mr_tmp;  in ddr_set_rate()  local
3428 	mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_INIT4);  in ddr_set_rate()
3437 			      (mr_tmp >> PCTL2_LPDDR234_MR3_SHIFT) &  in ddr_set_rate()
3456 			      ((mr_tmp >> PCTL2_DDR34_MR2_SHIFT) &  in ddr_set_rate()
3459 			pctl_write_mr(dram->pctl, 3, 3, mr_tmp & PCTL2_MR_MASK,  in ddr_set_rate()
3461 			mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in ddr_set_rate()
3464 				      (mr_tmp >> PCTL2_DDR4_MR4_SHIFT) &  in ddr_set_rate()
3468 				      mr_tmp >> PCTL2_DDR4_MR5_SHIFT &  in ddr_set_rate()
3472 			mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in ddr_set_rate()
3475 				      mr_tmp >> PCTL2_DDR4_MR6_SHIFT &  in ddr_set_rate()
3481 			      ((mr_tmp >> PCTL2_LPDDR4_MR13_SHIFT &  in ddr_set_rate()