895 	u32 mr1_mr3, mr11, mr22, vref_out, vref_inner;  in set_ds_odt()  local
1087 		mr1_mr3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1089 		mr1_mr3 = mr1_mr3 >> PCTL2_DDR34_MR1_SHIFT & PCTL2_MR_MASK;  in set_ds_odt()
1091 		mr1_mr3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1093 		mr1_mr3 = mr1_mr3 >> PCTL2_LPDDR234_MR3_SHIFT & PCTL2_MR_MASK;  in set_ds_odt()
1097 		mr1_mr3 &= ~(DDR3_DS_MASK | DDR3_RTT_NOM_MASK);  in set_ds_odt()
1099 			mr1_mr3 |= DDR3_DS_34;  in set_ds_odt()
1102 			mr1_mr3 |= DDR3_RTT_NOM_DIS;  in set_ds_odt()
1104 			mr1_mr3 |= DDR3_RTT_NOM_40;  in set_ds_odt()
1106 			mr1_mr3 |= DDR3_RTT_NOM_60;  in set_ds_odt()
1108 			mr1_mr3 |= DDR3_RTT_NOM_120;  in set_ds_odt()
1111 		mr1_mr3 &= ~(DDR4_DS_MASK | DDR4_RTT_NOM_MASK);  in set_ds_odt()
1113 			mr1_mr3 |= DDR4_DS_48;  in set_ds_odt()
1116 			mr1_mr3 |= DDR4_RTT_NOM_DIS;  in set_ds_odt()
1118 			mr1_mr3 |= DDR4_RTT_NOM_34;  in set_ds_odt()
1120 			mr1_mr3 |= DDR4_RTT_NOM_40;  in set_ds_odt()
1122 			mr1_mr3 |= DDR4_RTT_NOM_48;  in set_ds_odt()
1124 			mr1_mr3 |= DDR4_RTT_NOM_60;  in set_ds_odt()
1126 			mr1_mr3 |= DDR4_RTT_NOM_120;  in set_ds_odt()
1130 			mr1_mr3 |= LPDDR3_DS_34;  in set_ds_odt()
1132 			mr1_mr3 |= LPDDR3_DS_40;  in set_ds_odt()
1134 			mr1_mr3 |= LPDDR3_DS_48;  in set_ds_odt()
1136 			mr1_mr3 |= LPDDR3_DS_60;  in set_ds_odt()
1138 			mr1_mr3 |= LPDDR3_DS_80;  in set_ds_odt()
1150 		mr1_mr3 &= ~(LPDDR4_PDDS_MASK | LPDDR4_PU_CAL_MASK);  in set_ds_odt()
1151 		mr1_mr3 |= lp4_pu_cal;  in set_ds_odt()
1156 		mr1_mr3 |= (tmp << LPDDR4_PDDS_SHIFT);  in set_ds_odt()
1206 				mr1_mr3 << PCTL2_DDR34_MR1_SHIFT);  in set_ds_odt()
1213 				mr1_mr3 << PCTL2_LPDDR234_MR3_SHIFT);  in set_ds_odt()