807 			 u32 freq_mhz, u32 dst_fsp, u32 dramtype)  in set_lp4_vref()  argument
865 	clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_lp4_vref()
870 	clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_lp4_vref()
878 		       struct rv1126_sdram_params *sdram_params, u32 dst_fsp)  in set_ds_odt()  argument
1084 		set_lp4_vref(dram, lp4_info, freq, dst_fsp, dramtype);  in set_ds_odt()
1087 		mr1_mr3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1091 		mr1_mr3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1159 		mr11 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1171 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1178 		mr22 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1194 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1203 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1210 		clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in set_ds_odt()
1809 			    u32 mhz, u32 dst_fsp)  in data_training_wr()  argument
1901 		fsp_param[dst_fsp].vref_dq[cs] =  in data_training_wr()
1905 		fsp_param[dst_fsp].vref_dq[cs] |=  in data_training_wr()
1922 			 struct rv1126_sdram_params *sdram_params, u32 dst_fsp,  in data_training()  argument
1957 				       sdram_params->base.ddr_freq, dst_fsp);  in data_training()
2938 			 u32 dst_fsp, u32 dst_fsp_lp4)  in pre_set_rate()  argument
2955 				       pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
2966 	tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_RFSHTMG);  in pre_set_rate()
2969 	       pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_RFSHTMG);  in pre_set_rate()
2975 	if (dst_fsp == 0)  in pre_set_rate()
2978 		phy_offset = PHY_REG(0, 0x387 - 5 + (dst_fsp - 1) * 3);  in pre_set_rate()
2994 	set_ds_odt(dram, sdram_params, dst_fsp);  in pre_set_rate()
2996 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3015 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3030 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3043 		mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in pre_set_rate()
3062 static void save_fsp_param(struct dram_info *dram, u32 dst_fsp,  in save_fsp_param()  argument
3067 	struct rv1126_fsp_param *p_fsp_param = &fsp_param[dst_fsp];  in save_fsp_param()
3099 		temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in save_fsp_param()
3106 		temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in save_fsp_param()
3113 		temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in save_fsp_param()
3122 		temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in save_fsp_param()
3127 		temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in save_fsp_param()
3308 		  u32 freq, u32 cur_freq, u32 dst_fsp,  in ddr_set_rate()  argument
3327 	pre_set_rate(dram, sdram_params_new, dst_fsp, dst_fsp_lp4);  in ddr_set_rate()
3335 	dst_init3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in ddr_set_rate()
3380 	setbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_ZQCTL0,  in ddr_set_rate()
3418 	clrsetbits_le32(pctl_base + DDR_PCTL2_MSTR2, 0x3, dst_fsp);  in ddr_set_rate()
3421 	clrsetbits_le32(PHY_REG(phy_base, 0xc), 0x3 << 2, dst_fsp << 2);  in ddr_set_rate()
3428 	mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_INIT4);  in ddr_set_rate()
3461 			mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in ddr_set_rate()
3472 			mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) +  in ddr_set_rate()
3490 	high_freq_training(dram, sdram_params_new, dst_fsp);  in ddr_set_rate()
3493 	save_fsp_param(dram, dst_fsp, sdram_params_new);  in ddr_set_rate()