393 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in calculate_ddrconfig()  local
400 	cs = cap_info->rank;  in calculate_ddrconfig()
401 	bw = cap_info->bw;  in calculate_ddrconfig()
402 	die_bw = cap_info->dbw;  in calculate_ddrconfig()
403 	col = cap_info->col;  in calculate_ddrconfig()
404 	row = cap_info->cs0_row;  in calculate_ddrconfig()
405 	cs1_row = cap_info->cs1_row;  in calculate_ddrconfig()
406 	bank = cap_info->bk;  in calculate_ddrconfig()
407 	row_3_4 = cap_info->row_3_4;  in calculate_ddrconfig()
520 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in set_ctl_address_map()  local
522 	u32 ddrconf = cap_info->ddrconfig;  in set_ctl_address_map()
525 	row = cap_info->cs0_row;  in set_ctl_address_map()
549 	if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4)  in set_ctl_address_map()
551 	if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1)  in set_ctl_address_map()
554 	if (cap_info->rank == 1)  in set_ctl_address_map()
1244 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in phy_cfg()  local
1273 	if (cap_info->bw == 2)  in phy_cfg()
1275 	else if (cap_info->bw == 1)  in phy_cfg()
1934 				       sdram_params->ch.cap_info.rank);  in data_training()
1981 	if (sdram_params->ch.cap_info.rank == 2)  in get_wrlvl_val()
2094 	for (j = 0; j < sdram_params->ch.cap_info.rank; j++) {  in high_freq_training()
2101 		   (int)(sdram_params->ch.cap_info.rank * (1 << sdram_params->ch.cap_info.bw));  in high_freq_training()
2108 		for (j = 0; j < sdram_params->ch.cap_info.rank; j++)  in high_freq_training()
2141 	if (sdram_params->ch.cap_info.rank == 2) {  in high_freq_training()
2161 				sdram_params->ch.cap_info.rank) * -1;  in high_freq_training()
2163 			 min_val, min_val, sdram_params->ch.cap_info.rank);  in high_freq_training()
2171 				    sdram_params->ch.cap_info.rank),  in high_freq_training()
2173 				    sdram_params->ch.cap_info.rank)) * -1;  in high_freq_training()
2180 			 min_val, min_val, sdram_params->ch.cap_info.rank);  in high_freq_training()
2188 	if (sdram_params->ch.cap_info.rank == 2)  in high_freq_training()
2207 	bw = 8 << sdram_params->ch.cap_info.bw;  in update_noc_timing()
2247 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in split_setup()  local
2252 	cs_cap[0] = sdram_get_cs_cap(cap_info, 0, dramtype);  in split_setup()
2253 	cs_cap[1] = sdram_get_cs_cap(cap_info, 1, dramtype);  in split_setup()
2255 	if (cap_info->cs0_high16bit_row < cap_info->cs0_row) {  in split_setup()
2256 		cap = cs_cap[0] / (1 << (cap_info->cs0_row -  in split_setup()
2257 		cap_info->cs0_high16bit_row));  in split_setup()
2258 	} else if ((cap_info->cs1_high16bit_row < cap_info->cs1_row) &&  in split_setup()
2259 		   (cap_info->rank == 2)) {  in split_setup()
2260 		if (!cap_info->cs1_high16bit_row)  in split_setup()
2263 			cap = cs_cap[0] + cs_cap[1] / (1 << (cap_info->cs1_row -  in split_setup()
2264 				cap_info->cs1_high16bit_row));  in split_setup()
2269 	if (cap_info->bw == 2)  in split_setup()
2307 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in dram_all_config()  local
2315 	set_ddrconfig(dram, cap_info->ddrconfig);  in dram_all_config()
2316 	sdram_org_config(cap_info, &sdram_params->base, &sys_reg2,  in dram_all_config()
2321 	cs_cap[0] = sdram_get_cs_cap(cap_info, 0, dram_type);  in dram_all_config()
2322 	cs_cap[1] = sdram_get_cs_cap(cap_info, 1, dram_type);  in dram_all_config()
2324 	if (cap_info->rank == 2) {  in dram_all_config()
2371 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in ddr_set_atags()  local
2382 	cs_cap[0] = sdram_get_cs_cap(cap_info, 0, dram_type);  in ddr_set_atags()
2383 	cs_cap[1] = sdram_get_cs_cap(cap_info, 1, dram_type);  in ddr_set_atags()
2399 	if (cap_info->row_3_4) {  in ddr_set_atags()
2443 	sdram_print_ddr_info(&sdram_params->ch.cap_info,  in print_ddr_info()
2452 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in modify_ddr34_bw_byte_map()  local
2478 	cap_info->bw = byte / 2;  in modify_ddr34_bw_byte_map()
2489 		pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info, dramtype);  in modify_ddr34_bw_byte_map()
2519 	if (sdram_params->ch.cap_info.bw == 2) {  in sdram_init_()
2543 	sdram_params->ch.cap_info.ddrconfig = calculate_ddrconfig(sdram_params);  in sdram_init_()
2613 	if (post_init != 0 && sdram_params->ch.cap_info.rank == 2) {  in sdram_init_()
2637 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in dram_detect_cap()  local
2663 			if (sdram_detect_col(cap_info, coltmp) != 0)  in dram_detect_cap()
2666 			sdram_detect_bank(cap_info, coltmp, bktmp);  in dram_detect_cap()
2668 				sdram_detect_dbw(cap_info, dram_type);  in dram_detect_cap()
2674 			cap_info->col = 10;  in dram_detect_cap()
2675 			cap_info->bk = 2;  in dram_detect_cap()
2676 			sdram_detect_bg(cap_info, coltmp);  in dram_detect_cap()
2679 		if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0)  in dram_detect_cap()
2682 		sdram_detect_row_3_4(cap_info, coltmp, bktmp);  in dram_detect_cap()
2684 		cap_info->col = 10;  in dram_detect_cap()
2685 		cap_info->bk = 3;  in dram_detect_cap()
2687 		cap_info->dbw = ((mr8 >> 6) & 0x3) == 0 ? 1 : 0;  in dram_detect_cap()
2690 			cap_info->cs0_row = 14 + (mr8 + 1) / 2;  in dram_detect_cap()
2692 			cap_info->cs0_row = 13;  in dram_detect_cap()
2697 		if (cap_info->dbw == 0)  in dram_detect_cap()
2698 			cap_info->cs0_row++;  in dram_detect_cap()
2699 		cap_info->row_3_4 = mr8 % 2 == 1 ? 1 : 0;  in dram_detect_cap()
2700 		if (cap_info->cs0_row >= 17) {  in dram_detect_cap()
2716 	cap_info->rank = cs + 1;  in dram_detect_cap()
2722 			cap_info->bw = 2;  in dram_detect_cap()
2734 				cap_info->bw = 1;  in dram_detect_cap()
2736 				cap_info->bw = 0;  in dram_detect_cap()
2739 	if (cap_info->bw > 0)  in dram_detect_cap()
2740 		cap_info->dbw = 1;  in dram_detect_cap()
2744 	cap_info->cs0_high16bit_row = cap_info->cs0_row;  in dram_detect_cap()
2746 		cap_info->cs1_row = cap_info->cs0_row;  in dram_detect_cap()
2747 		cap_info->cs1_high16bit_row = cap_info->cs0_row;  in dram_detect_cap()
2749 		cap_info->cs1_row = 0;  in dram_detect_cap()
2750 		cap_info->cs1_high16bit_row = 0;  in dram_detect_cap()
2754 		sdram_detect_dbw(cap_info, dram_type);  in dram_detect_cap()
2765 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in dram_detect_cs1_row()  local
2776 	if (cap_info->rank == 2) {  in dram_detect_cs1_row()
2785 			if (cap_info->dbw == 0)  in dram_detect_cs1_row()
2786 				bktmp = cap_info->bk + 2;  in dram_detect_cs1_row()
2788 				bktmp = cap_info->bk + 1;  in dram_detect_cs1_row()
2790 			bktmp = cap_info->bk;  in dram_detect_cs1_row()
2792 		bw = cap_info->bw;  in dram_detect_cs1_row()
2793 		coltmp = cap_info->col;  in dram_detect_cs1_row()
2804 		row = (cap_info->cs0_row > max_row) ? max_row :  in dram_detect_cs1_row()
2805 			cap_info->cs0_row;  in dram_detect_cs1_row()
2833 	struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;  in sdram_init_detect()  local
2857 	pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info,  in sdram_init_detect()
2863 	cap_info->cs1_row =  in sdram_init_detect()
2865 	if (cap_info->cs1_row) {  in sdram_init_detect()
2868 		SYS_REG_ENC_CS1_ROW(cap_info->cs1_row,  in sdram_init_detect()
2874 	sdram_detect_high_row(cap_info, sdram_params->base.dramtype);  in sdram_init_detect()
3187 			     struct sdram_cap_info *cap_info, u32 dram_type,  in pctl_modify_trfc()  argument
3197 	cs0_cap = sdram_get_cs_cap(cap_info, 0, dram_type);  in pctl_modify_trfc()
3198 	die_cap = (u32)(cs0_cap >> (20 + (cap_info->bw - cap_info->dbw)));  in pctl_modify_trfc()
3322 	sdram_params_new->ch.cap_info.rank = sdram_params->ch.cap_info.rank;  in ddr_set_rate()
3323 	sdram_params_new->ch.cap_info.bw = sdram_params->ch.cap_info.bw;  in ddr_set_rate()
3326 			 &sdram_params->ch.cap_info, dramtype, freq);  in ddr_set_rate()
3635 				  (u8)sdram_params->ch.cap_info.rank);  in sdram_init()