Lines Matching full:dram
303 static void rkclk_ddr_reset(struct dram_info *dram, in rkclk_ddr_reset() argument
312 &dram->cru->softrst_con[12]); in rkclk_ddr_reset()
315 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) in rkclk_set_dpll() argument
351 writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode); in rkclk_set_dpll()
353 writel(0x1f000000, &dram->cru->clksel_con[64]); in rkclk_set_dpll()
354 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); in rkclk_set_dpll()
358 clrsetbits_le32(&dram->cru->pll[1].con2, in rkclk_set_dpll()
366 &dram->cru->pll[1].con3); in rkclk_set_dpll()
369 &dram->cru->pll[1].con1); in rkclk_set_dpll()
373 if (LOCK(readl(&dram->cru->pll[1].con1))) in rkclk_set_dpll()
380 writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode); in rkclk_set_dpll()
383 static void rkclk_configure_ddr(struct dram_info *dram, in rkclk_configure_ddr() argument
387 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ / 2); in rkclk_configure_ddr()
495 static void sw_set_req(struct dram_info *dram) in sw_set_req() argument
497 void __iomem *pctl_base = dram->pctl; in sw_set_req()
503 static void sw_set_ack(struct dram_info *dram) in sw_set_ack() argument
505 void __iomem *pctl_base = dram->pctl; in sw_set_ack()
517 static void set_ctl_address_map(struct dram_info *dram, in set_ctl_address_map() argument
521 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map()
558 static void phy_pll_set(struct dram_info *dram, u32 freq, u32 wait) in phy_pll_set() argument
560 void __iomem *phy_base = dram->phy; in phy_pll_set()
802 printascii("unsupported dram type\n"); in get_ddr_drv_odt_info()
806 static void set_lp4_vref(struct dram_info *dram, struct lp4_info *lp4_info, in set_lp4_vref() argument
809 void __iomem *pctl_base = dram->pctl; in set_lp4_vref()
864 sw_set_req(dram); in set_lp4_vref()
874 sw_set_ack(dram); in set_lp4_vref()
877 static void set_ds_odt(struct dram_info *dram, in set_ds_odt() argument
880 void __iomem *phy_base = dram->phy; in set_ds_odt()
881 void __iomem *pctl_base = dram->pctl; in set_ds_odt()
906 /* dram odt en freq control phy drv, dram odt and phy sr */ in set_ds_odt()
930 /* phy odt en freq control dram drv and phy odt */ in set_ds_odt()
1084 set_lp4_vref(dram, lp4_info, freq, dst_fsp, dramtype); in set_ds_odt()
1170 sw_set_req(dram); in set_ds_odt()
1175 sw_set_ack(dram); in set_ds_odt()
1193 sw_set_req(dram); in set_ds_odt()
1198 sw_set_ack(dram); in set_ds_odt()
1202 sw_set_req(dram); in set_ds_odt()
1207 sw_set_ack(dram); in set_ds_odt()
1209 sw_set_req(dram); in set_ds_odt()
1214 sw_set_ack(dram); in set_ds_odt()
1218 static int sdram_cmd_dq_path_remap(struct dram_info *dram, in sdram_cmd_dq_path_remap() argument
1221 void __iomem *phy_base = dram->phy; in sdram_cmd_dq_path_remap()
1241 static void phy_cfg(struct dram_info *dram, in phy_cfg() argument
1245 void __iomem *phy_base = dram->phy; in phy_cfg()
1249 sdram_cmd_dq_path_remap(dram, sdram_params); in phy_cfg()
1251 phy_pll_set(dram, sdram_params->base.ddr_freq * MHZ, 0); in phy_cfg()
1294 static int update_refresh_reg(struct dram_info *dram) in update_refresh_reg() argument
1296 void __iomem *pctl_base = dram->pctl; in update_refresh_reg()
1309 u32 read_mr(struct dram_info *dram, u32 rank, u32 mr_num, u32 dramtype) in read_mr() argument
1313 void __iomem *pctl_base = dram->pctl; in read_mr()
1324 temp = (readl(&dram->ddrgrf->ddr_grf_status[0]) & 0xff); in read_mr()
1329 ret = readl(&dram->ddrgrf->ddr_grf_status[1]) & 0xff; in read_mr()
1336 void send_a_refresh(struct dram_info *dram) in send_a_refresh() argument
1338 void __iomem *pctl_base = dram->pctl; in send_a_refresh()
1345 static void enter_sr(struct dram_info *dram, u32 en) in enter_sr() argument
1347 void __iomem *pctl_base = dram->pctl; in enter_sr()
1368 void record_dq_prebit(struct dram_info *dram) in record_dq_prebit() argument
1371 void __iomem *phy_base = dram->phy; in record_dq_prebit()
1392 static void update_dq_rx_prebit(struct dram_info *dram) in update_dq_rx_prebit() argument
1394 void __iomem *phy_base = dram->phy; in update_dq_rx_prebit()
1402 static void update_dq_tx_prebit(struct dram_info *dram) in update_dq_tx_prebit() argument
1404 void __iomem *phy_base = dram->phy; in update_dq_tx_prebit()
1413 static void update_ca_prebit(struct dram_info *dram) in update_ca_prebit() argument
1415 void __iomem *phy_base = dram->phy; in update_ca_prebit()
1429 static void modify_ca_deskew(struct dram_info *dram, u32 dir, int delta_dif, in modify_ca_deskew() argument
1432 void __iomem *phy_base = dram->phy; in modify_ca_deskew()
1448 enter_sr(dram, 1); in modify_ca_deskew()
1471 update_ca_prebit(dram); in modify_ca_deskew()
1473 enter_sr(dram, 0); in modify_ca_deskew()
1480 static u32 get_min_value(struct dram_info *dram, u32 signal, u32 rank) in get_min_value() argument
1484 void __iomem *phy_base = dram->phy; in get_min_value()
1509 static u32 low_power_update(struct dram_info *dram, u32 en) in low_power_update() argument
1511 void __iomem *pctl_base = dram->pctl; in low_power_update()
1531 static void modify_dq_deskew(struct dram_info *dram, u32 signal, u32 dir, in modify_dq_deskew() argument
1534 void __iomem *phy_base = dram->phy; in modify_dq_deskew()
1566 update_dq_rx_prebit(dram); in modify_dq_deskew()
1568 update_dq_tx_prebit(dram); in modify_dq_deskew()
1571 static int data_training_rg(struct dram_info *dram, u32 cs, u32 dramtype) in data_training_rg() argument
1573 void __iomem *phy_base = dram->phy; in data_training_rg()
1591 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training_rg()
1607 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training_rg()
1621 static int data_training_wl(struct dram_info *dram, u32 cs, u32 dramtype, in data_training_wl() argument
1624 void __iomem *pctl_base = dram->pctl; in data_training_wl()
1625 void __iomem *phy_base = dram->phy; in data_training_wl()
1631 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training_wl()
1642 pctl_write_mr(dram->pctl, (cs + 1) & 1, 1, tmp | (1 << 12), in data_training_wl()
1676 pctl_write_mr(dram->pctl, (cs + 1) & 1, 1, tmp & ~(1 << 12), in data_training_wl()
1679 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training_wl()
1691 static int data_training_rd(struct dram_info *dram, u32 cs, u32 dramtype, in data_training_rd() argument
1694 void __iomem *pctl_base = dram->pctl; in data_training_rd()
1695 void __iomem *phy_base = dram->phy; in data_training_rd()
1725 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training_rd()
1793 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training_rd()
1808 static int data_training_wr(struct dram_info *dram, u32 cs, u32 dramtype, in data_training_wr() argument
1811 void __iomem *pctl_base = dram->pctl; in data_training_wr()
1812 void __iomem *phy_base = dram->phy; in data_training_wr()
1827 pctl_write_mr(dram->pctl, 3, 2, 0x6, dramtype); in data_training_wr()
1830 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training_wr()
1874 send_a_refresh(dram); in data_training_wr()
1897 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training_wr()
1914 pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK, in data_training_wr()
1921 static int data_training(struct dram_info *dram, u32 cs, in data_training() argument
1932 ret = data_training_wl(dram, cs, in data_training()
1940 ret = data_training_rg(dram, cs, in data_training()
1947 ret = data_training_rd(dram, cs, in data_training()
1955 ret = data_training_wr(dram, cs, in data_training()
1966 static int get_wrlvl_val(struct dram_info *dram, in get_wrlvl_val() argument
1970 void __iomem *phy_base = dram->phy; in get_wrlvl_val()
1974 lp_stat = low_power_update(dram, 0); in get_wrlvl_val()
1977 modify_ca_deskew(dram, DESKEW_MDF_ABS_VAL, clk_skew, clk_skew, 3, in get_wrlvl_val()
1980 ret = data_training(dram, 0, sdram_params, 0, WRITE_LEVELING); in get_wrlvl_val()
1982 ret |= data_training(dram, 1, sdram_params, 0, WRITE_LEVELING); in get_wrlvl_val()
1990 low_power_update(dram, lp_stat); in get_wrlvl_val()
2080 static int high_freq_training(struct dram_info *dram, in high_freq_training() argument
2085 void __iomem *phy_base = dram->phy; in high_freq_training()
2126 modify_ca_deskew(dram, DESKEW_MDF_ABS_VAL, clk_skew, ca_skew, 3, in high_freq_training()
2133 ret = data_training(dram, 0, sdram_params, fsp, READ_GATE_TRAINING | in high_freq_training()
2146 ret |= data_training(dram, 1, sdram_params, fsp, in high_freq_training()
2158 record_dq_prebit(dram); in high_freq_training()
2160 min_val = get_min_value(dram, SKEW_RX_SIGNAL, in high_freq_training()
2162 modify_dq_deskew(dram, SKEW_RX_SIGNAL, DESKEW_MDF_DIFF_VAL, in high_freq_training()
2170 min_val = MIN(get_min_value(dram, SKEW_TX_SIGNAL, in high_freq_training()
2172 get_min_value(dram, SKEW_CA_SIGNAL, in high_freq_training()
2176 modify_ca_deskew(dram, DESKEW_MDF_DIFF_VAL, min_val, min_val, 3, in high_freq_training()
2179 modify_dq_deskew(dram, SKEW_TX_SIGNAL, DESKEW_MDF_DIFF_VAL, in high_freq_training()
2187 ret = data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING); in high_freq_training()
2189 ret |= data_training(dram, 1, sdram_params, 0, in high_freq_training()
2195 static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig) in set_ddrconfig() argument
2197 writel(ddrconfig, &dram->msch->deviceconf); in set_ddrconfig()
2198 clrsetbits_le32(&dram->grf->noc_con0, 0x3 << 0, 0 << 0); in set_ddrconfig()
2201 static void update_noc_timing(struct dram_info *dram, in update_noc_timing() argument
2204 void __iomem *pctl_base = dram->pctl; in update_noc_timing()
2232 &dram->msch->ddrtiminga0); in update_noc_timing()
2234 &dram->msch->ddrtimingb0); in update_noc_timing()
2236 &dram->msch->ddrtimingc0); in update_noc_timing()
2238 &dram->msch->devtodev0); in update_noc_timing()
2239 writel(sdram_params->ch.noc_timings.ddrmode.d32, &dram->msch->ddrmode); in update_noc_timing()
2241 &dram->msch->ddr4timing); in update_noc_timing()
2244 static int split_setup(struct dram_info *dram, in split_setup() argument
2274 rk_clrsetreg(&dram->ddrgrf->grf_ddrsplit_con, in split_setup()
2290 static void split_bypass(struct dram_info *dram) in split_bypass() argument
2292 if ((readl(&dram->ddrgrf->grf_ddrsplit_con) & in split_bypass()
2297 rk_clrsetreg(&dram->ddrgrf->grf_ddrsplit_con, in split_bypass()
2304 static void dram_all_config(struct dram_info *dram, in dram_all_config() argument
2309 void __iomem *pctl_base = dram->pctl; in dram_all_config()
2315 set_ddrconfig(dram, cap_info->ddrconfig); in dram_all_config()
2318 writel(sys_reg2, &dram->pmugrf->os_reg[2]); in dram_all_config()
2319 writel(sys_reg3, &dram->pmugrf->os_reg[3]); in dram_all_config()
2333 &dram->msch->devicesize); in dram_all_config()
2334 update_noc_timing(dram, sdram_params); in dram_all_config()
2337 static void enable_low_power(struct dram_info *dram, in enable_low_power() argument
2340 void __iomem *pctl_base = dram->pctl; in enable_low_power()
2343 writel(0x1f1f0617, &dram->ddrgrf->ddr_grf_con[1]); in enable_low_power()
2354 writel(grf_lp_con, &dram->ddrgrf->ddr_grf_lp_con); in enable_low_power()
2357 if (dram->pd_idle == 0) in enable_low_power()
2361 if (dram->sr_idle == 0) in enable_low_power()
2368 static void ddr_set_atags(struct dram_info *dram, in ddr_set_atags() argument
2373 void __iomem *pctl_base = dram->pctl; in ddr_set_atags()
2397 split = readl(&dram->ddrgrf->grf_ddrsplit_con); in ddr_set_atags()
2496 int sdram_init_(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 post_init) in sdram_init_() argument
2498 void __iomem *pctl_base = dram->pctl; in sdram_init_()
2499 void __iomem *phy_base = dram->phy; in sdram_init_()
2504 rkclk_configure_ddr(dram, sdram_params); in sdram_init_()
2506 rkclk_ddr_reset(dram, 1, 1, 1, 1); in sdram_init_()
2509 rkclk_ddr_reset(dram, 1, 1, 1, 0); in sdram_init_()
2510 phy_cfg(dram, sdram_params); in sdram_init_()
2512 rkclk_ddr_reset(dram, 1, 1, 0, 0); in sdram_init_()
2513 phy_pll_set(dram, sdram_params->base.ddr_freq * MHZ, 1); in sdram_init_()
2515 rkclk_ddr_reset(dram, 1, 0, 0, 0); in sdram_init_()
2516 pctl_cfg(dram->pctl, &sdram_params->pctl_regs, in sdram_init_()
2517 dram->sr_idle, dram->pd_idle); in sdram_init_()
2542 set_ds_odt(dram, sdram_params, 0); in sdram_init_()
2544 set_ctl_address_map(dram, sdram_params); in sdram_init_()
2548 rkclk_ddr_reset(dram, 0, 0, 0, 0); in sdram_init_()
2560 pctl_write_mr(dram->pctl, 3, 11, lp3_odt_value, LPDDR3); in sdram_init_()
2565 pctl_write_mr(dram->pctl, 3, 11, in sdram_init_()
2569 pctl_write_mr(dram->pctl, 3, 12, in sdram_init_()
2575 pctl_write_mr(dram->pctl, 3, 22, in sdram_init_()
2582 tmp = data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING) & 0xf; in sdram_init_()
2599 mr_tmp = read_mr(dram, 1, 14, LPDDR4); in sdram_init_()
2609 pctl_write_mr(dram->pctl, 3, 14, in sdram_init_()
2614 if (data_training(dram, 1, sdram_params, 0, in sdram_init_()
2623 pctl_write_vrefdq(dram->pctl, 0x3, ddr4_vref, in sdram_init_()
2627 dram_all_config(dram, sdram_params); in sdram_init_()
2628 enable_low_power(dram, sdram_params); in sdram_init_()
2633 static u64 dram_detect_cap(struct dram_info *dram, in dram_detect_cap() argument
2638 void __iomem *pctl_base = dram->pctl; in dram_detect_cap()
2639 void __iomem *phy_base = dram->phy; in dram_detect_cap()
2686 mr8 = read_mr(dram, 1, 8, dram_type); in dram_detect_cap()
2712 if (data_training(dram, 1, sdram_params, 0, READ_GATE_TRAINING) == 0) in dram_detect_cap()
2721 if ((data_training_rg(dram, 0, dram_type) & 0xf) == 0) { in dram_detect_cap()
2733 if (data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING) == 0) in dram_detect_cap()
2761 static int dram_detect_cs1_row(struct dram_info *dram, in dram_detect_cs1_row() argument
2766 void __iomem *pctl_base = dram->pctl; in dram_detect_cs1_row()
2830 static int sdram_init_detect(struct dram_info *dram, in sdram_init_detect() argument
2838 if (sdram_init_(dram, sdram_params, 0)) { in sdram_init_detect()
2840 if (sdram_init_(dram, sdram_params, 0)) in sdram_init_detect()
2853 split_bypass(dram); in sdram_init_detect()
2854 if (dram_detect_cap(dram, sdram_params, 0) != 0) in sdram_init_detect()
2859 ret = sdram_init_(dram, sdram_params, 1); in sdram_init_detect()
2864 dram_detect_cs1_row(dram, sdram_params, 0); in sdram_init_detect()
2866 sys_reg = readl(&dram->pmugrf->os_reg[2]); in sdram_init_detect()
2867 sys_reg3 = readl(&dram->pmugrf->os_reg[3]); in sdram_init_detect()
2870 writel(sys_reg, &dram->pmugrf->os_reg[2]); in sdram_init_detect()
2871 writel(sys_reg3, &dram->pmugrf->os_reg[3]); in sdram_init_detect()
2875 split_setup(dram, sdram_params); in sdram_init_detect()
2936 static void pre_set_rate(struct dram_info *dram, in pre_set_rate() argument
2941 void __iomem *pctl_base = dram->pctl; in pre_set_rate()
2942 void __iomem *phy_base = dram->phy; in pre_set_rate()
2947 sw_set_req(dram); in pre_set_rate()
2972 sw_set_ack(dram); in pre_set_rate()
2994 set_ds_odt(dram, sdram_params, dst_fsp); in pre_set_rate()
2999 pctl_write_mr(dram->pctl, 3, 13, in pre_set_rate()
3008 pctl_write_mr(dram->pctl, 3, 3, in pre_set_rate()
3018 pctl_write_mr(dram->pctl, 3, 1, in pre_set_rate()
3025 pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK, in pre_set_rate()
3033 pctl_write_mr(dram->pctl, 3, 11, in pre_set_rate()
3039 pctl_write_mr(dram->pctl, 3, 12, in pre_set_rate()
3046 pctl_write_mr(dram->pctl, 3, 22, in pre_set_rate()
3052 pctl_write_mr(dram->pctl, 3, 14, in pre_set_rate()
3059 update_noc_timing(dram, sdram_params); in pre_set_rate()
3062 static void save_fsp_param(struct dram_info *dram, u32 dst_fsp, in save_fsp_param() argument
3065 void __iomem *pctl_base = dram->pctl; in save_fsp_param()
3066 void __iomem *phy_base = dram->phy; in save_fsp_param()
3306 void ddr_set_rate(struct dram_info *dram, in ddr_set_rate() argument
3316 void __iomem *pctl_base = dram->pctl; in ddr_set_rate()
3317 void __iomem *phy_base = dram->phy; in ddr_set_rate()
3320 lp_stat = low_power_update(dram, 0); in ddr_set_rate()
3327 pre_set_rate(dram, sdram_params_new, dst_fsp, dst_fsp_lp4); in ddr_set_rate()
3355 pctl_write_mr(dram->pctl, 2, 1, cur_init3, dramtype); in ddr_set_rate()
3360 update_refresh_reg(dram); in ddr_set_rate()
3362 enter_sr(dram, 1); in ddr_set_rate()
3366 &dram->pmugrf->soc_con[0]); in ddr_set_rate()
3367 sw_set_req(dram); in ddr_set_rate()
3370 sw_set_ack(dram); in ddr_set_rate()
3372 sw_set_req(dram); in ddr_set_rate()
3382 sw_set_ack(dram); in ddr_set_rate()
3385 &dram->cru->clkgate_con[21]); in ddr_set_rate()
3392 rkclk_set_dpll(dram, freq * MHz / 2); in ddr_set_rate()
3393 phy_pll_set(dram, freq * MHz, 0); in ddr_set_rate()
3394 phy_pll_set(dram, freq * MHz, 1); in ddr_set_rate()
3399 &dram->pmugrf->soc_con[0]); in ddr_set_rate()
3401 &dram->cru->clkgate_con[21]); in ddr_set_rate()
3416 sw_set_req(dram); in ddr_set_rate()
3419 sw_set_ack(dram); in ddr_set_rate()
3420 update_refresh_reg(dram); in ddr_set_rate()
3423 enter_sr(dram, 0); in ddr_set_rate()
3430 pctl_write_mr(dram->pctl, 3, 1, in ddr_set_rate()
3434 pctl_write_mr(dram->pctl, 3, 2, dst_init3 & PCTL2_MR_MASK, in ddr_set_rate()
3436 pctl_write_mr(dram->pctl, 3, 3, in ddr_set_rate()
3440 pctl_write_mr(dram->pctl, 3, 11, lp3_odt_value, dramtype); in ddr_set_rate()
3442 pctl_write_mr(dram->pctl, 3, 1, dst_init3 & PCTL2_MR_MASK, in ddr_set_rate()
3445 pctl_write_mr(dram->pctl, 3, 0, in ddr_set_rate()
3451 pctl_write_mr(dram->pctl, 3, 0, in ddr_set_rate()
3455 pctl_write_mr(dram->pctl, 3, 2, in ddr_set_rate()
3459 pctl_write_mr(dram->pctl, 3, 3, mr_tmp & PCTL2_MR_MASK, in ddr_set_rate()
3463 pctl_write_mr(dram->pctl, 3, 4, in ddr_set_rate()
3467 pctl_write_mr(dram->pctl, 3, 5, in ddr_set_rate()
3474 pctl_write_mr(dram->pctl, 3, 6, in ddr_set_rate()
3480 pctl_write_mr(dram->pctl, 3, 13, in ddr_set_rate()
3487 update_refresh_reg(dram); in ddr_set_rate()
3490 high_freq_training(dram, sdram_params_new, dst_fsp); in ddr_set_rate()
3491 low_power_update(dram, lp_stat); in ddr_set_rate()
3493 save_fsp_param(dram, dst_fsp, sdram_params_new); in ddr_set_rate()
3496 static void ddr_set_rate_for_fsp(struct dram_info *dram, in ddr_set_rate_for_fsp() argument
3525 if (get_wrlvl_val(dram, sdram_params)) in ddr_set_rate_for_fsp()