78 #include "sdram-rk3399-lpddr4-400.inc"
79 #include "sdram-rk3399-lpddr4-800.inc"
179 	if (sdram_params->base.dramtype == LPDDR4) {  in set_memory_map()
220 	if (sdram_params->base.dramtype == LPDDR4) {  in phy_io_config()
222 			/* MODE_LV[2:0] = LPDDR4 (Range 2)*/  in phy_io_config()
224 			/* MODE[2:0]= LPDDR4 Range 2(0.4*VDDQ) */  in phy_io_config()
228 			/* MODE_LV[2:0] = LPDDR4 (Range 1)*/  in phy_io_config()
230 			/* MODE[2:0]= LPDDR4 Range 1(0.33*VDDQ) */  in phy_io_config()
327 	if (sdram_params->base.dramtype == LPDDR4) {  in phy_io_config()
350 	if (sdram_params->base.dramtype == LPDDR4) {  in phy_io_config()
399 	if (sdram_params->base.dramtype == LPDDR4) {  in phy_io_config()
559 	if (sdram_params->base.dramtype == LPDDR4) {  in set_ds_odt()
598 			printf("LPDDR4 MR22 Soc ODT not support\n");  in set_ds_odt()
637 	if (sdram_params->base.dramtype == LPDDR4) {  in set_ds_odt()
693 	if (sdram_params->base.dramtype == LPDDR4) {  in set_ds_odt()
694 		/* LPDDR4 these register read always return 0, so  in set_ds_odt()
767 	if (sdram_params->base.dramtype == LPDDR4)  in set_ds_odt()
864 		if (sdram_params->base.dramtype == LPDDR4)  in pctl_start()
1197 	if (sdram_params->base.dramtype == LPDDR4) {  in modify_param()
1268 	if (sdram_params->base.dramtype == LPDDR4 && channel == 1) {  in pctl_cfg()
1284 	if (sdram_params->base.dramtype == LPDDR4) {  in pctl_cfg()
1301 	/* because LPDDR4 use PLL bypass mode for init  in pctl_cfg()
1304 	if (sdram_params->base.dramtype != LPDDR4) {  in pctl_cfg()
1333 	if (sdram_params->base.dramtype == LPDDR4)  in pctl_cfg()
1359 	if (sdram_params->base.dramtype == LPDDR4) {  in pctl_cfg()
1442 	if (sdram_params->base.dramtype == LPDDR4)  in data_training_ca()
1664 	if (sdram_params->base.dramtype == LPDDR4)  in data_training_wdql()
1716 		if (sdram_params->base.dramtype == LPDDR4) {  in data_training()
1730 	/* ca training(LPDDR4,LPDDR3 support) */  in data_training()
1737 	/* write leveling(LPDDR4,LPDDR3,DDR3 support) */  in data_training()
1744 	/* read gate training(LPDDR4,LPDDR3,DDR3 support) */  in data_training()
1751 	/* read leveling(LPDDR4,LPDDR3,DDR3 support) */  in data_training()
1758 	/* wdq leveling(LPDDR4 support) */  in data_training()
2170 	if (dramtype == LPDDR4) {  in dram_set_cs()
2279 	if (sdram_params->base.dramtype != LPDDR4) {  in dram_detect_cap()
2303 	if (sdram_params->base.dramtype != LPDDR4) {  in dram_detect_cap()
2485 	if (sdram_params->base.dramtype == LPDDR4)  in get_phy_fn()
2495 	if (sdram_params->base.dramtype == LPDDR4)  in get_ctl_fn()
2765 	if (f1_sdram_params->base.dramtype == LPDDR4) {  in dram_copy_phy_fn()
2873 	/* LPDDR4 f2 can not do training, all training will fail */  in dram_set_rate()
2874 	if (!(sdram_params->base.dramtype == LPDDR4 && fn == 2)) {  in dram_set_rate()
2940 	    (dramtype == LPDDR4 && ddr_freq > 800)) {  in sdram_init()
2971 			if (sdram_params->base.dramtype == LPDDR4) {  in sdram_init()
2983 				 * LPDDR4 need confirm here!  in sdram_init()
3046 	if (sdram_params->base.dramtype != LPDDR4)  in sdram_init()
3049 	if (sdram_params->base.dramtype == LPDDR4) {  in sdram_init()