237 	} else if (sdram_params->base.dramtype == LPDDR3) {  in phy_io_config()
238 		/* LPDDR3 */  in phy_io_config()
240 			vref_mode_dq = 0x5;  /*LPDDR3 ODT*/  in phy_io_config()
605 	} else if (sdram_params->base.dramtype == LPDDR3) {  in set_ds_odt()
1720 		} else if (sdram_params->base.dramtype == LPDDR3) {  in data_training()
1730 	/* ca training(LPDDR4,LPDDR3 support) */  in data_training()
1737 	/* write leveling(LPDDR4,LPDDR3,DDR3 support) */  in data_training()
1744 	/* read gate training(LPDDR4,LPDDR3,DDR3 support) */  in data_training()
1751 	/* read leveling(LPDDR4,LPDDR3,DDR3 support) */  in data_training()
2115 	if (sdram_params->base.dramtype == LPDDR3) {  in set_cap_relate_config()
2295 	 * LPDDR3 CA training msut be trigger before other training.  in dram_detect_cap()
2298 	if (sdram_params->base.dramtype == LPDDR3)  in dram_detect_cap()
2939 	    (dramtype == LPDDR3 && ddr_freq > 933) ||  in sdram_init()
2963 			/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */  in sdram_init()
2964 			if (dramtype == LPDDR3)  in sdram_init()
2980 				 * LPDDR3 CA training msut be trigger before  in sdram_init()
2985 				if (sdram_params->base.dramtype == LPDDR3)  in sdram_init()