Lines Matching +full:pctrl +full:- +full:syscon
4 * SPDX-License-Identifier: GPL-2.0
10 #include <dt-structs.h>
13 #include <syscon.h>
54 struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat; in conv_of_platdata()
57 ret = regmap_init_mem_platdata(dev, dtplat->reg, in conv_of_platdata()
58 ARRAY_SIZE(dtplat->reg) / 2, in conv_of_platdata()
59 &plat->map); in conv_of_platdata()
73 &dram->cru->softrst_con[5]); in rkclk_ddr_reset()
74 writel(ddrctrl_asrstn_req(ctl_srstn), &dram->cru->softrst_con[9]); in rkclk_ddr_reset()
105 writel(((0x1 << 4) << 16) | (0 << 4), &dram->cru->mode_con); in rkclk_set_dpll()
106 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]); in rkclk_set_dpll()
108 &dram->cru->dpll_con[1]); in rkclk_set_dpll()
112 if (LOCK(readl(&dram->cru->dpll_con[1]))) in rkclk_set_dpll()
114 delay--; in rkclk_set_dpll()
117 writel(((0x1 << 4) << 16) | (1 << 4), &dram->cru->mode_con); in rkclk_set_dpll()
123 void __iomem *phy_base = dram->phy; in rkclk_configure_ddr()
129 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ * 2); in rkclk_configure_ddr()
133 * (-1), find ddrconfig fail
140 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in calculate_ddrconfig()
144 u32 ddrconf = -1; in calculate_ddrconfig()
146 cs = cap_info->rank; in calculate_ddrconfig()
147 bw = cap_info->bw; in calculate_ddrconfig()
148 die_bw = cap_info->dbw; in calculate_ddrconfig()
149 col = cap_info->col; in calculate_ddrconfig()
150 row = cap_info->cs0_row; in calculate_ddrconfig()
151 cs1_row = cap_info->cs1_row; in calculate_ddrconfig()
152 bank = cap_info->bk; in calculate_ddrconfig()
154 if (sdram_params->base.dramtype == DDR4) { in calculate_ddrconfig()
157 /* include 2cs cap both 2^n or both (2^n - 2^(n-2)) */ in calculate_ddrconfig()
158 tmp = ((row - 13) << 3) | (1 << 2) | (bw & 0x2) | in calculate_ddrconfig()
162 (ddr4_cfg_2_rbc[i - 10] & 0x7)) && in calculate_ddrconfig()
164 (ddr4_cfg_2_rbc[i - 10] & 0x3c))) { in calculate_ddrconfig()
171 tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw; in calculate_ddrconfig()
173 if (((tmp & 0x7) == (ddr4_cfg_2_rbc[i - 10] & 0x7)) && in calculate_ddrconfig()
174 ((tmp & 0x3c) <= (ddr4_cfg_2_rbc[i - 10] & 0x3c)) && in calculate_ddrconfig()
175 ((tmp & 0x40) <= (ddr4_cfg_2_rbc[i - 10] & 0x40))) { in calculate_ddrconfig()
188 /* include 2cs cap both 2^n or both (2^n - 2^(n-2)) */ in calculate_ddrconfig()
190 if ((bw + col - 11) == (ddr_cfg_2_rbc[i] & in calculate_ddrconfig()
198 tmp = ((row - 13) << 4) | (1 << 2) | ((bw + col - 11) << 0); in calculate_ddrconfig()
222 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in set_ctl_address_map()
223 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map()
226 &addrmap[cap_info->ddrconfig][0], 9 * 4); in set_ctl_address_map()
227 if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4) in set_ctl_address_map()
229 if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1) in set_ctl_address_map()
232 if (cap_info->rank == 1) in set_ctl_address_map()
238 void __iomem *pctl_base = dram->pctl; in data_training()
243 /* disable auto low-power */ in data_training()
247 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training()
249 ret = phy_data_training(dram->phy, cs, dramtype); in data_training()
251 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training()
253 /* restore auto low-power */ in data_training()
263 void __iomem *phy_base = dram->phy; in rx_deskew_switch_adjust()
277 void __iomem *phy_base = dram->phy; in tx_deskew_switch_adjust()
284 writel(ddrconfig, &dram->msch->ddrconf); in set_ddrconfig()
290 writel(noc_timings->ddrtiming.d32, &msch->ddrtiming); in sdram_msch_config()
292 writel(noc_timings->ddrmode.d32, &msch->ddrmode); in sdram_msch_config()
293 writel(noc_timings->readlatency, &msch->readlatency); in sdram_msch_config()
295 writel(noc_timings->activate.d32, &msch->activate); in sdram_msch_config()
296 writel(noc_timings->devtodev.d32, &msch->devtodev); in sdram_msch_config()
297 writel(noc_timings->ddr4timing.d32, &msch->ddr4_timing); in sdram_msch_config()
298 writel(noc_timings->agingx0, &msch->aging0); in sdram_msch_config()
299 writel(noc_timings->agingx0, &msch->aging1); in sdram_msch_config()
300 writel(noc_timings->agingx0, &msch->aging2); in sdram_msch_config()
301 writel(noc_timings->agingx0, &msch->aging3); in sdram_msch_config()
302 writel(noc_timings->agingx0, &msch->aging4); in sdram_msch_config()
303 writel(noc_timings->agingx0, &msch->aging5); in sdram_msch_config()
309 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in dram_all_config()
313 set_ddrconfig(dram, cap_info->ddrconfig); in dram_all_config()
314 sdram_org_config(cap_info, &sdram_params->base, &sys_reg2, in dram_all_config()
316 writel(sys_reg2, &dram->grf->os_reg[2]); in dram_all_config()
317 writel(sys_reg3, &dram->grf->os_reg[3]); in dram_all_config()
319 sdram_msch_config(dram->msch, &sdram_ch.noc_timings); in dram_all_config()
325 void __iomem *pctl_base = dram->pctl; in enable_low_power()
328 writel(0x00800000, &dram->ddr_grf->ddr_grf_con[0]); in enable_low_power()
329 writel(0x20012001, &dram->ddr_grf->ddr_grf_con[2]); in enable_low_power()
331 writel(0x001e001a, &dram->ddr_grf->ddr_grf_con[2]); in enable_low_power()
347 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in sdram_init()
348 void __iomem *pctl_base = dram->pctl; in sdram_init()
363 phy_soft_reset(dram->phy); in sdram_init()
366 pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE); in sdram_init()
367 cap_info->ddrconfig = calculate_ddrconfig(sdram_params); in sdram_init()
369 phy_cfg(dram->phy, &sdram_params->phy_regs, &sdram_params->skew, in sdram_init()
370 &sdram_params->base, cap_info->bw); in sdram_init()
380 if (data_training(dram, 0, sdram_params->base.dramtype) != 0) { in sdram_init()
382 return -1; in sdram_init()
384 if (data_training(dram, 1, sdram_params->base.dramtype) != 0) { in sdram_init()
386 return -1; in sdram_init()
389 if (sdram_params->base.dramtype == DDR4) in sdram_init()
390 pctl_write_vrefdq(dram->pctl, 0x3, 5670, in sdram_init()
391 sdram_params->base.dramtype); in sdram_init()
408 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in dram_detect_cap()
421 u32 dram_type = sdram_params->base.dramtype; in dram_detect_cap()
441 cap_info->col = col; in dram_detect_cap()
442 cap_info->bk = bk; in dram_detect_cap()
458 cap_info->rank = cs + 1; in dram_detect_cap()
461 cap_info->bw = bw; in dram_detect_cap()
463 cap_info->cs0_high16bit_row = cap_info->cs0_row; in dram_detect_cap()
465 cap_info->cs1_row = cap_info->cs0_row; in dram_detect_cap()
466 cap_info->cs1_high16bit_row = cap_info->cs0_row; in dram_detect_cap()
468 cap_info->cs1_row = 0; in dram_detect_cap()
469 cap_info->cs1_high16bit_row = 0; in dram_detect_cap()
474 return -1; in dram_detect_cap()
482 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in sdram_init_detect()
486 memcpy(&sdram_ch, &sdram_params->ch, in sdram_init_detect()
493 pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info, in sdram_init_detect()
494 sdram_params->base.dramtype); in sdram_init_detect()
496 if (cap_info->bw == 2) in sdram_init_detect()
505 sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype); in sdram_init_detect()
506 if (cap_info->cs1_row) { in sdram_init_detect()
507 sys_reg = readl(&dram->grf->os_reg[2]); in sdram_init_detect()
508 sys_reg3 = readl(&dram->grf->os_reg[3]); in sdram_init_detect()
509 SYS_REG_ENC_CS1_ROW(cap_info->cs1_row, in sdram_init_detect()
511 writel(sys_reg, &dram->grf->os_reg[2]); in sdram_init_detect()
512 writel(sys_reg3, &dram->grf->os_reg[3]); in sdram_init_detect()
515 sdram_print_ddr_info(&sdram_params->ch.cap_info, in sdram_init_detect()
516 &sdram_params->base, 0); in sdram_init_detect()
528 struct rk3328_sdram_params *params = &plat->sdram_params; in rk3328_dmc_init()
530 struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat; in rk3328_dmc_init()
532 (void *)dtplat->rockchip_sdram_params; in rk3328_dmc_init()
538 priv->phy = regmap_get_range(plat->map, 0); in rk3328_dmc_init()
539 priv->pctl = regmap_get_range(plat->map, 1); in rk3328_dmc_init()
540 priv->grf = regmap_get_range(plat->map, 2); in rk3328_dmc_init()
541 priv->cru = regmap_get_range(plat->map, 3); in rk3328_dmc_init()
542 priv->msch = regmap_get_range(plat->map, 4); in rk3328_dmc_init()
543 priv->ddr_grf = regmap_get_range(plat->map, 5); in rk3328_dmc_init()
545 debug("%s phy %p pctrl %p grf %p cru %p msch %p ddr_grf %p\n", in rk3328_dmc_init()
546 __func__, priv->phy, priv->pctl, priv->grf, priv->cru, in rk3328_dmc_init()
547 priv->msch, priv->ddr_grf); in rk3328_dmc_init()
563 ret = dev_read_u32_array(dev, "rockchip,sdram-params", in rk3328_dmc_ofdata_to_platdata()
564 (u32 *)&plat->sdram_params, in rk3328_dmc_ofdata_to_platdata()
565 sizeof(plat->sdram_params) / sizeof(u32)); in rk3328_dmc_ofdata_to_platdata()
567 printf("%s: Cannot read rockchip,sdram-params %d\n", in rk3328_dmc_ofdata_to_platdata()
571 ret = regmap_init_mem(dev, &plat->map); in rk3328_dmc_ofdata_to_platdata()
589 if (!(gd->flags & GD_FLG_RELOC)) { in rk3328_dmc_probe()
591 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3328_dmc_probe()
592 debug("%s: grf=%p\n", __func__, priv->grf); in rk3328_dmc_probe()
593 priv->info.base = CONFIG_SYS_SDRAM_BASE; in rk3328_dmc_probe()
594 priv->info.size = in rk3328_dmc_probe()
595 rockchip_sdram_size((phys_addr_t)&priv->grf->os_reg[2]); in rk3328_dmc_probe()
600 ddr_parem.para[0] = priv->info.base; in rk3328_dmc_probe()
601 ddr_parem.para[1] = priv->info.size; in rk3328_dmc_probe()
617 *info = priv->info; in rk3328_dmc_get_info()
627 { .compatible = "rockchip,rk3328-dmc" },