27 #define CRU_BASE		0xff500000
28 #define GRF_BASE		0xff000000
29 #define SGRF_BASE		0xff2b0000
30 #define DDR_PHY_BASE		0xff530000
31 #define DDR_PCTL_BASE		0xff010000
32 #define DDR_STANDBY_BASE	0xff030000
33 #define PMU_BASS_ADDR		0xff520000
34 #define SERVICE_MSCH_BASE	0xff5c8000
136 	rk3308_pll_div.frac = 0x872B02;  in rkdclk_init()
137 	rk3308_pll_div.dsmpd = 0;  in rkdclk_init()
146 		rk3308_pll_div.frac = 0x24DD2F;  in rkdclk_init()
147 		rk3308_pll_div.dsmpd = 0;  in rkdclk_init()
154 		rk3308_pll_div.frac = 0x9BA5E3;  in rkdclk_init()
155 		rk3308_pll_div.dsmpd = 0;  in rkdclk_init()
160 		ddr_pll_sel = 0;  in rkdclk_init()
161 		ddr_phy_div_con = 0;  in rkdclk_init()
164 		ddr_phy_div_con = 0;  in rkdclk_init()
167 		ddr_phy_div_con = 0;  in rkdclk_init()
170 		ddr_phy_div_con = 0;  in rkdclk_init()
190 		rk3308_pll_div.frac = 0;  in rkdclk_init()
198 		rk3308_pll_div.frac = 0;  in rkdclk_init()
267 	rk3308_pll_div.frac = 0;  in rkdclk_init()
330 	rk3308_pll_div.frac = 0;  in rkdclk_init()
395 		uart_div[UART_INFO_ID(ddr_gd.head_info.g_uart_info)] = 0;  in rkdclk_init()
400 		     uart_div[0] << CLK_UART0_DIV_CON_SHIFT);  in rkdclk_init()
475 	int i = 0;  in ddr_msch_cfg_rbc()
488 		i = 0;  in ddr_msch_cfg_rbc()
504 	copy_to_reg(&priv->phy->phy_reg_ca_skew[0],  in ddr_phy_skew_cfg()
505 		    &ddr_gd.ddr_skew.a0_a1_skew[0], 14 * 4);  in ddr_phy_skew_cfg()
506 	copy_to_reg(&priv->phy->phy_reg_skew_cs0data[0],  in ddr_phy_skew_cfg()
507 		    &ddr_gd.ddr_skew.cs0_dm0_skew[0], 22 * 4);  in ddr_phy_skew_cfg()
615 	memset(&t_serial, 0, sizeof(struct tag_serial));  in ddr_set_atags()
619 	t_serial.version = 0;  in ddr_set_atags()
622 		t_serial.enable = 0;  in ddr_set_atags()
628 		if (UART_INFO_ID(uart_info) == 0)  in ddr_set_atags()
642 	t_serial.version = 0;  in ddr_set_atags()
647 #if (CONFIG_DEBUG_UART_BASE == 0xFF0A0000)  in ddr_set_atags()
650 	t_serial.id = 0;  in ddr_set_atags()
651 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0B0000)  in ddr_set_atags()
655 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0C0000)  in ddr_set_atags()
656 #if (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in ddr_set_atags()
665 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0D0000)  in ddr_set_atags()
669 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0E0000)  in ddr_set_atags()
688 	u32 tmp = 0;  in modify_sdram_params()
700 		if (size <= 0x4000000)  in modify_sdram_params()
702 		else if (size <= 0x8000000)  in modify_sdram_params()
704 		else if (size <= 0x10000000)  in modify_sdram_params()
713 		priv->pctl->texsr = tmp & 0x3FF;  in modify_sdram_params()
716 		if (size <= 0x4000000)  in modify_sdram_params()
718 		else if (size <= 0x8000000)  in modify_sdram_params()
720 		else if (size <= 0x10000000)  in modify_sdram_params()
722 		else if (size <= 0x20000000)  in modify_sdram_params()
729 		if (size <= 0x4000000)  in modify_sdram_params()
731 		else if (size <= 0x20000000)  in modify_sdram_params()
740 		priv->pctl->texsr = tmp & 0x3FF;  in modify_sdram_params()
748 	u32 max_val = 0;  in check_rd_gate()
749 	u32 min_val = 0xff;  in check_rd_gate()
752 	gate[0] = readl(&priv->phy->phy_regfb);  in check_rd_gate()
754 	max_val = max(gate[0], gate[1]);  in check_rd_gate()
755 	min_val = min(gate[0], gate[1]);  in check_rd_gate()
757 	if (max_val > 0x80 || min_val < 0x20)  in check_rd_gate()
760 		return 0;  in check_rd_gate()
765 	for (phys_addr_t j = 4 * dqs; j < 0x2000; j += 8)  in dram_test()
768 	for (phys_addr_t j = 4 * dqs; j < 0x2000; j += 8)  in dram_test()
772 	return 0;  in dram_test()
779 #define PHY_REG3C(n)		(0x10 * (n))
784 	u32 value = 0;  in modify_data_training()
785 	u32 i = 0, dqs = 0;  in modify_data_training()
786 	u32 max_value = 0, min_value = 0;  in modify_data_training()
795 	for (dqs = 0; dqs < 2; dqs++) {  in modify_data_training()
797 		i = 0;  in modify_data_training()
798 		while (dram_test(i, dqs) == 0) {  in modify_data_training()
807 		while (dram_test(i, dqs) == 0) {  in modify_data_training()
818 	printascii("REG2C: 0x");  in modify_data_training()
820 	printascii(", 0x");  in modify_data_training()
876 	if (params->idle_pd != 0 && params->idle_sr != 0)  in sdram_init()
881 	return 0;  in sdram_init()
886 /* return: 0 = success, other = fail */