Lines Matching refs:publ
34 struct rk3288_ddr_publ *publ; member
123 struct rk3288_ddr_publ *publ, in phy_pctrl_reset() argument
130 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
132 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
135 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
137 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
146 static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ, in phy_dll_bypass_set() argument
153 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
155 setbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
156 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); in phy_dll_bypass_set()
158 setbits_le32(&publ->datx8[i].dxdllcr, in phy_dll_bypass_set()
161 setbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
163 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
164 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); in phy_dll_bypass_set()
166 clrbits_le32(&publ->datx8[i].dxdllcr, in phy_dll_bypass_set()
170 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
295 struct rk3288_ddr_publ *publ = chan->publ; in phy_cfg() local
303 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, in phy_cfg()
312 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); in phy_cfg()
315 &publ->ptr[1]); in phy_cfg()
318 &publ->ptr[2]); in phy_cfg()
322 clrsetbits_le32(&publ->pgcr, 0x1F, in phy_cfg()
328 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, in phy_cfg()
330 clrsetbits_le32(&publ->dxccr, in phy_cfg()
334 tmp = readl(&publ->dtpr[1]); in phy_cfg()
337 clrsetbits_le32(&publ->dsgcr, in phy_cfg()
343 clrbits_le32(&publ->pgcr, 0x1f); in phy_cfg()
344 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, in phy_cfg()
351 setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); in phy_cfg()
355 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); in phy_cfg()
359 static void phy_init(struct rk3288_ddr_publ *publ) in phy_init() argument
361 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST in phy_init()
364 while ((readl(&publ->pgsr) & in phy_init()
386 static void memory_init(struct rk3288_ddr_publ *publ, in memory_init() argument
389 setbits_le32(&publ->pir, in memory_init()
394 while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) in memory_init()
399 static void move_to_config_state(struct rk3288_ddr_publ *publ, in move_to_config_state() argument
414 while ((readl(&publ->pgsr) & PGSR_DLDONE) in move_to_config_state()
441 struct rk3288_ddr_publ *publ = chan->publ; in set_bandwidth_ratio() local
449 clrbits_le32(&publ->datx8[2].dxgcr, 1); in set_bandwidth_ratio()
450 clrbits_le32(&publ->datx8[3].dxgcr, 1); in set_bandwidth_ratio()
452 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
453 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
459 setbits_le32(&publ->datx8[2].dxgcr, 1); in set_bandwidth_ratio()
460 setbits_le32(&publ->datx8[3].dxgcr, 1); in set_bandwidth_ratio()
463 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
464 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
466 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
467 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
469 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
470 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
483 struct rk3288_ddr_publ *publ = chan->publ; in data_training() local
490 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); in data_training()
497 setbits_le32(&publ->pir, PIR_CLRSR); in data_training()
500 setbits_le32(&publ->pir, in data_training()
505 while ((readl(&publ->datx8[0].dxgsr[0]) & rank) in data_training()
508 while ((readl(&publ->datx8[1].dxgsr[0]) & rank) in data_training()
512 while ((readl(&publ->datx8[2].dxgsr[0]) in data_training()
515 while ((readl(&publ->datx8[3].dxgsr[0]) in data_training()
519 if (readl(&publ->pgsr) & in data_training()
530 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); in data_training()
540 struct rk3288_ddr_publ *publ = chan->publ; in move_to_access_state() local
557 while ((readl(&publ->pgsr) & PGSR_DLDONE) in move_to_access_state()
581 struct rk3288_ddr_publ *publ = chan->publ; in dram_cfg_rbc() local
584 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, in dram_cfg_rbc()
587 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); in dram_cfg_rbc()
626 struct rk3288_ddr_publ *publ = chan->publ; in sdram_rank_bw_detect() local
629 reg = readl(&publ->datx8[0].dxgsr[0]); in sdram_rank_bw_detect()
642 clrsetbits_le32(&publ->pgcr, 0xF << 18, in sdram_rank_bw_detect()
646 reg = readl(&publ->datx8[2].dxgsr[0]); in sdram_rank_bw_detect()
680 struct rk3288_ddr_publ *publ = chan->publ; in sdram_col_row_detect() local
701 move_to_config_state(publ, pctl); in sdram_col_row_detect()
810 struct rk3288_ddr_publ *publ = chan->publ; in sdram_init() local
817 phy_pctrl_reset(dram->cru, publ, channel); in sdram_init()
818 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); in sdram_init()
826 phy_init(publ); in sdram_init()
832 memory_init(publ, sdram_params->base.dramtype); in sdram_init()
833 move_to_config_state(publ, pctl); in sdram_init()
864 clrsetbits_le32(&publ->pgcr, 0xF << 18, in sdram_init()
871 writel(zqcr, &publ->zq1cr[0]); in sdram_init()
872 writel(zqcr, &publ->zq0cr[0]); in sdram_init()
1067 priv->chan[0].publ = regmap_get_range(plat->map, 1); in rk3288_dmc_probe()
1069 priv->chan[1].publ = regmap_get_range(plat->map, 3); in rk3288_dmc_probe()