33 	struct rk3288_ddr_pctl *pctl;  member
174 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)  in dfi_cfg()  argument
176 	writel(DFI_INIT_START, &pctl->dfistcfg0);  in dfi_cfg()
178 	       &pctl->dfistcfg1);  in dfi_cfg()
179 	writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);  in dfi_cfg()
181 	       &pctl->dfilpcfg0);  in dfi_cfg()
183 	writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);  in dfi_cfg()
184 	writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);  in dfi_cfg()
185 	writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);  in dfi_cfg()
186 	writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);  in dfi_cfg()
187 	writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);  in dfi_cfg()
188 	writel(1, &pctl->dfitphyupdtype0);  in dfi_cfg()
192 	       &pctl->dfiodtcfg);  in dfi_cfg()
194 	writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);  in dfi_cfg()
196 	writel(0, &pctl->dfiupdcfg);  in dfi_cfg()
242 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,  in pctl_cfg()  argument
249 	copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,  in pctl_cfg()
254 		       &pctl->dfitrddataen);  in pctl_cfg()
256 		       &pctl->dfitphywrlat);  in pctl_cfg()
262 		       &pctl->mcfg);  in pctl_cfg()
271 			       &pctl->dfitrddataen);  in pctl_cfg()
274 			       &pctl->dfitrddataen);  in pctl_cfg()
277 		       &pctl->dfitphywrlat);  in pctl_cfg()
281 		       &pctl->mcfg);  in pctl_cfg()
289 	setbits_le32(&pctl->scfg, 1);  in pctl_cfg()
370 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank,  in send_command()  argument
373 	writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);  in send_command()
375 	while (readl(&pctl->mcmd) & START_CMD)  in send_command()
379 static inline void send_command_op(struct rk3288_ddr_pctl *pctl,  in send_command_op()  argument
382 	send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |  in send_command_op()
400 				 struct rk3288_ddr_pctl *pctl)  in move_to_config_state()  argument
405 		state = readl(&pctl->stat) & PCTL_STAT_MSK;  in move_to_config_state()
409 			writel(WAKEUP_STATE, &pctl->sctl);  in move_to_config_state()
410 			while ((readl(&pctl->stat) & PCTL_STAT_MSK)  in move_to_config_state()
425 			writel(CFG_STATE, &pctl->sctl);  in move_to_config_state()
426 			while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)  in move_to_config_state()
440 	struct rk3288_ddr_pctl *pctl = chan->pctl;  in set_bandwidth_ratio()  local
445 		setbits_le32(&pctl->ppcfg, 1);  in set_bandwidth_ratio()
455 		clrbits_le32(&pctl->ppcfg, 1);  in set_bandwidth_ratio()
472 	setbits_le32(&pctl->dfistcfg0, 1 << 2);  in set_bandwidth_ratio()
484 	struct rk3288_ddr_pctl *pctl = chan->pctl;  in data_training()  local
487 	writel(0, &pctl->trefi);  in data_training()
511 		if (!(readl(&pctl->ppcfg) & 1)) {  in data_training()
527 		send_command(pctl, rank, REF_CMD, 0);  in data_training()
533 	writel(sdram_params->pctl_timing.trefi, &pctl->trefi);  in data_training()
541 	struct rk3288_ddr_pctl *pctl = chan->pctl;  in move_to_access_state()  local
545 		state = readl(&pctl->stat) & PCTL_STAT_MSK;  in move_to_access_state()
549 			if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &  in move_to_access_state()
553 			writel(WAKEUP_STATE, &pctl->sctl);  in move_to_access_state()
554 			while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)  in move_to_access_state()
562 			writel(CFG_STATE, &pctl->sctl);  in move_to_access_state()
563 			while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)  in move_to_access_state()
566 			writel(GO_STATE, &pctl->sctl);  in move_to_access_state()
567 			while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)  in move_to_access_state()
679 	struct rk3288_ddr_pctl *pctl = chan->pctl;  in sdram_col_row_detect()  local
701 	move_to_config_state(publ, pctl);  in sdram_col_row_detect()
809 		struct rk3288_ddr_pctl *pctl = chan->pctl;  in sdram_init()  local
820 		dfi_cfg(pctl, sdram_params->base.dramtype);  in sdram_init()
822 		pctl_cfg(channel, pctl, sdram_params, dram->grf);  in sdram_init()
828 		writel(POWER_UP_START, &pctl->powctl);  in sdram_init()
829 		while (!(readl(&pctl->powstat) & POWER_UP_DONE))  in sdram_init()
833 		move_to_config_state(publ, pctl);  in sdram_init()
836 			send_command(pctl, 3, DESELECT_CMD, 0);  in sdram_init()
838 			send_command(pctl, 3, PREA_CMD, 0);  in sdram_init()
840 			send_command_op(pctl, 3, MRS_CMD, 63, 0xfc);  in sdram_init()
842 			send_command_op(pctl, 3, MRS_CMD, 1,  in sdram_init()
845 			send_command_op(pctl, 3, MRS_CMD, 2,  in sdram_init()
848 			send_command_op(pctl, 3, MRS_CMD, 3,  in sdram_init()
877 			send_command_op(pctl,  in sdram_init()
882 				writel(0, &pctl->mrrcfg0);  in sdram_init()
883 				send_command_op(pctl, 1, MRR_CMD, 8, 0);  in sdram_init()
885 				if ((readl(&pctl->mrrstat0) & 0x3) != 3) {  in sdram_init()
897 			writel(0, &pctl->mrrcfg0);  in sdram_init()
899 				send_command_op(pctl, 1, MRR_CMD, i, 0);  in sdram_init()
1066 	priv->chan[0].pctl = regmap_get_range(plat->map, 0);  in rk3288_dmc_probe()
1068 	priv->chan[1].pctl = regmap_get_range(plat->map, 2);  in rk3288_dmc_probe()