32 	struct rk3288_ddr_publ *publ;  member
124 			    struct rk3288_ddr_publ *publ,  in phy_pctrl_reset()  argument
131 	clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);  in phy_pctrl_reset()
133 		clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);  in phy_pctrl_reset()
136 	setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);  in phy_pctrl_reset()
138 		setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);  in phy_pctrl_reset()
147 static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ,  in phy_dll_bypass_set()  argument
154 			clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);  in phy_dll_bypass_set()
156 			setbits_le32(&publ->dllgcr, SBIAS_BYPASS);  in phy_dll_bypass_set()
157 		setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);  in phy_dll_bypass_set()
159 			setbits_le32(&publ->datx8[i].dxdllcr,  in phy_dll_bypass_set()
162 		setbits_le32(&publ->pir, PIR_DLLBYP);  in phy_dll_bypass_set()
164 		clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);  in phy_dll_bypass_set()
165 		clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);  in phy_dll_bypass_set()
167 			clrbits_le32(&publ->datx8[i].dxdllcr,  in phy_dll_bypass_set()
171 		clrbits_le32(&publ->pir, PIR_DLLBYP);  in phy_dll_bypass_set()
261 	struct rk3288_ddr_publ *publ = chan->publ;  in phy_cfg()  local
269 	copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,  in phy_cfg()
275 	       8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);  in phy_cfg()
278 	       &publ->ptr[1]);  in phy_cfg()
281 	       &publ->ptr[2]);  in phy_cfg()
285 		clrbits_le32(&publ->pgcr, 0x1f);  in phy_cfg()
286 		clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,  in phy_cfg()
293 			setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);  in phy_cfg()
297 			clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);  in phy_cfg()
301 static void phy_init(struct rk3288_ddr_publ *publ)  in phy_init()  argument
303 	setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST  in phy_init()
306 	while ((readl(&publ->pgsr) &  in phy_init()
328 static void memory_init(struct rk3288_ddr_publ *publ,  in memory_init()  argument
331 	setbits_le32(&publ->pir,  in memory_init()
336 	while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))  in memory_init()
341 static void move_to_config_state(struct rk3288_ddr_publ *publ,  in move_to_config_state()  argument
356 			while ((readl(&publ->pgsr) & PGSR_DLDONE)  in move_to_config_state()
383 	struct rk3288_ddr_publ *publ = chan->publ;  in set_bandwidth_ratio()  local
391 		clrbits_le32(&publ->datx8[2].dxgcr, 1);  in set_bandwidth_ratio()
392 		clrbits_le32(&publ->datx8[3].dxgcr, 1);  in set_bandwidth_ratio()
394 		setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);  in set_bandwidth_ratio()
395 		setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);  in set_bandwidth_ratio()
401 		setbits_le32(&publ->datx8[2].dxgcr, 1);  in set_bandwidth_ratio()
402 		setbits_le32(&publ->datx8[3].dxgcr, 1);  in set_bandwidth_ratio()
405 		clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);  in set_bandwidth_ratio()
406 		clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);  in set_bandwidth_ratio()
408 		clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);  in set_bandwidth_ratio()
409 		clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);  in set_bandwidth_ratio()
411 		setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);  in set_bandwidth_ratio()
412 		setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);  in set_bandwidth_ratio()
425 	struct rk3288_ddr_publ *publ = chan->publ;  in data_training()  local
432 		setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);  in data_training()
439 		setbits_le32(&publ->pir, PIR_CLRSR);  in data_training()
442 		setbits_le32(&publ->pir,  in data_training()
447 		while ((readl(&publ->datx8[0].dxgsr[0]) & rank)  in data_training()
450 		while ((readl(&publ->datx8[1].dxgsr[0]) & rank)  in data_training()
454 			while ((readl(&publ->datx8[2].dxgsr[0])  in data_training()
457 			while ((readl(&publ->datx8[3].dxgsr[0])  in data_training()
461 		if (readl(&publ->pgsr) &  in data_training()
472 		clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);  in data_training()
482 	struct rk3288_ddr_publ *publ = chan->publ;  in move_to_access_state()  local
499 			while ((readl(&publ->pgsr) & PGSR_DLDONE)  in move_to_access_state()
524 	struct rk3288_ddr_publ *publ = chan->publ;  in dram_cfg_rbc()  local
527 		clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,  in dram_cfg_rbc()
530 		clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);  in dram_cfg_rbc()
573 	struct rk3288_ddr_publ *publ = chan->publ;  in sdram_rank_bw_detect()  local
579 		reg = readl(&publ->datx8[0].dxgsr[0]);  in sdram_rank_bw_detect()
589 			clrsetbits_le32(&publ->pgcr, 0xF << 18,  in sdram_rank_bw_detect()
593 		reg = readl(&publ->datx8[2].dxgsr[0]);  in sdram_rank_bw_detect()
635 	struct rk3288_ddr_publ *publ = chan->publ;  in sdram_col_row_detect()  local
657 	move_to_config_state(publ, pctl);  in sdram_col_row_detect()
734 		struct rk3288_ddr_publ *publ = chan->publ;  in sdram_init()  local
736 		phy_pctrl_reset(dram->cru, publ, channel);  in sdram_init()
737 		phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);  in sdram_init()
745 		phy_init(publ);  in sdram_init()
751 		memory_init(publ, sdram_params->base.dramtype);  in sdram_init()
752 		move_to_config_state(publ, pctl);  in sdram_init()
765 		clrsetbits_le32(&publ->pgcr, 0xF << 18,  in sdram_init()
772 		writel(zqcr, &publ->zq1cr[0]);  in sdram_init()
773 		writel(zqcr, &publ->zq0cr[0]);  in sdram_init()
904 	priv->chan[0].publ = regmap_get_range(plat->map, 1);  in rk3188_dmc_probe()