Lines Matching refs:pctl
31 struct rk3288_ddr_pctl *pctl; member
175 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) in dfi_cfg() argument
177 writel(DFI_INIT_START, &pctl->dfistcfg0); in dfi_cfg()
179 &pctl->dfistcfg1); in dfi_cfg()
180 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); in dfi_cfg()
182 &pctl->dfilpcfg0); in dfi_cfg()
184 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); in dfi_cfg()
185 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); in dfi_cfg()
186 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); in dfi_cfg()
187 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); in dfi_cfg()
188 writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); in dfi_cfg()
189 writel(1, &pctl->dfitphyupdtype0); in dfi_cfg()
193 &pctl->dfiodtcfg); in dfi_cfg()
195 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); in dfi_cfg()
197 writel(0, &pctl->dfiupdcfg); in dfi_cfg()
229 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, in pctl_cfg() argument
233 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
239 &pctl->dfitrddataen); in pctl_cfg()
242 &pctl->dfitrddataen); in pctl_cfg()
245 &pctl->dfitphywrlat); in pctl_cfg()
249 &pctl->mcfg); in pctl_cfg()
255 setbits_le32(&pctl->scfg, 1); in pctl_cfg()
312 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, in send_command() argument
315 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
317 while (readl(&pctl->mcmd) & START_CMD) in send_command()
321 static inline void send_command_op(struct rk3288_ddr_pctl *pctl, in send_command_op() argument
324 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | in send_command_op()
342 struct rk3288_ddr_pctl *pctl) in move_to_config_state() argument
347 state = readl(&pctl->stat) & PCTL_STAT_MSK; in move_to_config_state()
351 writel(WAKEUP_STATE, &pctl->sctl); in move_to_config_state()
352 while ((readl(&pctl->stat) & PCTL_STAT_MSK) in move_to_config_state()
367 writel(CFG_STATE, &pctl->sctl); in move_to_config_state()
368 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) in move_to_config_state()
382 struct rk3288_ddr_pctl *pctl = chan->pctl; in set_bandwidth_ratio() local
387 setbits_le32(&pctl->ppcfg, 1); in set_bandwidth_ratio()
397 clrbits_le32(&pctl->ppcfg, 1); in set_bandwidth_ratio()
414 setbits_le32(&pctl->dfistcfg0, 1 << 2); in set_bandwidth_ratio()
426 struct rk3288_ddr_pctl *pctl = chan->pctl; in data_training() local
429 writel(0, &pctl->trefi); in data_training()
453 if (!(readl(&pctl->ppcfg) & 1)) { in data_training()
469 send_command(pctl, rank, REF_CMD, 0); in data_training()
475 writel(sdram_params->pctl_timing.trefi, &pctl->trefi); in data_training()
483 struct rk3288_ddr_pctl *pctl = chan->pctl; in move_to_access_state() local
487 state = readl(&pctl->stat) & PCTL_STAT_MSK; in move_to_access_state()
491 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & in move_to_access_state()
495 writel(WAKEUP_STATE, &pctl->sctl); in move_to_access_state()
496 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) in move_to_access_state()
504 writel(CFG_STATE, &pctl->sctl); in move_to_access_state()
505 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) in move_to_access_state()
509 writel(GO_STATE, &pctl->sctl); in move_to_access_state()
510 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) in move_to_access_state()
634 struct rk3288_ddr_pctl *pctl = chan->pctl; in sdram_col_row_detect() local
657 move_to_config_state(publ, pctl); in sdram_col_row_detect()
733 struct rk3288_ddr_pctl *pctl = chan->pctl; in sdram_init() local
739 dfi_cfg(pctl, sdram_params->base.dramtype); in sdram_init()
741 pctl_cfg(channel, pctl, sdram_params, dram->grf); in sdram_init()
747 writel(POWER_UP_START, &pctl->powctl); in sdram_init()
748 while (!(readl(&pctl->powstat) & POWER_UP_DONE)) in sdram_init()
752 move_to_config_state(publ, pctl); in sdram_init()
781 writel(0, &pctl->mrrcfg0); in sdram_init()
783 send_command_op(pctl, 1, MRR_CMD, i, 0); in sdram_init()
903 priv->chan[0].pctl = regmap_get_range(plat->map, 0); in rk3188_dmc_probe()