Lines Matching refs:pctl_base
173 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map() local
189 writel(0x1f, pctl_base + DDR_PCTL2_ADDRMAP0); in set_ctl_address_map()
191 writel(cs_pst - 8, pctl_base + DDR_PCTL2_ADDRMAP0); in set_ctl_address_map()
203 sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP1), in set_ctl_address_map()
211 clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6 + in set_ctl_address_map()
219 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31); in set_ctl_address_map()
221 setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8); in set_ctl_address_map()
276 void __iomem *pctl_base = dram->pctl; in data_training() local
282 pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL); in data_training()
283 writel(0, pctl_base + DDR_PCTL2_PWRCTL); in data_training()
292 writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL); in data_training()
358 void __iomem *pctl_base = dram->pctl; in enable_low_power() local
390 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); in enable_low_power()
392 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); in enable_low_power()
394 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); in enable_low_power()
396 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); in enable_low_power()
397 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3)); in enable_low_power()
411 void __iomem *pctl_base = dram->pctl; in sdram_init_() local
436 setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4)); in sdram_init_()
440 while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0) in sdram_init_()