65 static void rkclk_ddr_reset(struct dram_info *dram,  in rkclk_ddr_reset()  argument
71 	       &dram->cru->softrst_con[1]);  in rkclk_ddr_reset()
73 	       &dram->cru->softrst_con[2]);  in rkclk_ddr_reset()
76 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz)  in rkclk_set_dpll()  argument
104 	writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode);  in rkclk_set_dpll()
106 	writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0);  in rkclk_set_dpll()
108 	       &dram->cru->pll[1].con1);  in rkclk_set_dpll()
112 		if (LOCK(readl(&dram->cru->pll[1].con1)))  in rkclk_set_dpll()
117 	writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode);  in rkclk_set_dpll()
120 static void rkclk_configure_ddr(struct dram_info *dram,  in rkclk_configure_ddr()  argument
124 	rkclk_set_dpll(dram,  sdram_params->base.ddr_freq * MHz * 2);  in rkclk_configure_ddr()
165  * calculate controller dram address map, and setting to register.
169 static void set_ctl_address_map(struct dram_info *dram,  in set_ctl_address_map()  argument
173 	void __iomem *pctl_base = dram->pctl;  in set_ctl_address_map()
179 		 * DDR4 8bit dram BG = 2(4bank groups),  in set_ctl_address_map()
180 		 * 16bit dram BG = 1 (2 bank groups)  in set_ctl_address_map()
228 int read_mr(struct dram_info *dram, u32 rank, u32 mr_num)  in read_mr()  argument
230 	void __iomem *ddr_grf_base = dram->ddr_grf;  in read_mr()
232 	pctl_read_mr(dram->pctl, rank, mr_num);  in read_mr()
239 static u32 check_rd_gate(struct dram_info *dram)  in check_rd_gate()  argument
241 	void __iomem *phy_base = dram->phy;  in check_rd_gate()
274 static int data_training(struct dram_info *dram, u32 cs, u32 dramtype)  in data_training()  argument
276 	void __iomem *pctl_base = dram->pctl;  in data_training()
285 	dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl);  in data_training()
287 	ret = phy_data_training(dram->phy, cs, dramtype);  in data_training()
289 	pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq);  in data_training()
297 static void dram_set_bw(struct dram_info *dram, u32 bw)  in dram_set_bw()  argument
299 	phy_dram_set_bw(dram->phy, bw);  in dram_set_bw()
302 static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig)  in set_ddrconfig()  argument
304 	writel(ddrconfig | (ddrconfig << 8), &dram->msch->deviceconf);  in set_ddrconfig()
305 	rk_clrsetreg(&dram->grf->soc_noc_con[1], 0x3 << 14, 0 << 14);  in set_ddrconfig()
339 static void dram_all_config(struct dram_info *dram,  in dram_all_config()  argument
346 	set_ddrconfig(dram, cap_info->ddrconfig);  in dram_all_config()
349 	writel(sys_reg2, &dram->pmugrf->os_reg[2]);  in dram_all_config()
350 	writel(sys_reg3, &dram->pmugrf->os_reg[3]);  in dram_all_config()
351 	sdram_msch_config(dram->msch, &sdram_params->ch.noc_timings, cap_info,  in dram_all_config()
355 static void enable_low_power(struct dram_info *dram,  in enable_low_power()  argument
358 	void __iomem *pctl_base = dram->pctl;  in enable_low_power()
359 	void __iomem *phy_base = dram->phy;  in enable_low_power()
360 	void __iomem *ddr_grf_base = dram->ddr_grf;  in enable_low_power()
372 	writel(0x1f1f0617, &dram->ddr_grf->ddr_grf_con[1]);  in enable_low_power()
401  * pre_init: 0: pre init for dram cap detect
405  *    to reinit dram, than set the correct ddrconf.
407 static int sdram_init_(struct dram_info *dram,  in sdram_init_()  argument
411 	void __iomem *pctl_base = dram->pctl;  in sdram_init_()
413 	rkclk_ddr_reset(dram, 1, 1, 1, 1);  in sdram_init_()
420 	rkclk_ddr_reset(dram, 1, 1, 1, 0);  in sdram_init_()
421 	rkclk_configure_ddr(dram, sdram_params);  in sdram_init_()
424 	rkclk_ddr_reset(dram, 1, 1, 0, 0);  in sdram_init_()
426 	phy_soft_reset(dram->phy);  in sdram_init_()
428 	rkclk_ddr_reset(dram, 1, 0, 0, 0);  in sdram_init_()
429 	pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE);  in sdram_init_()
431 	set_ctl_address_map(dram, sdram_params);  in sdram_init_()
432 	phy_cfg(dram->phy, &sdram_params->phy_regs, sdram_params->skew,  in sdram_init_()
438 	rkclk_ddr_reset(dram, 0, 0, 0, 0);  in sdram_init_()
439 	/* wait for dfi_init_done and dram init complete */  in sdram_init_()
444 		pctl_write_mr(dram->pctl, 3, 11, 3, LPDDR3);  in sdram_init_()
448 	if (data_training(dram, 0, sdram_params->base.dramtype) != 0) {  in sdram_init_()
453 	if (check_rd_gate(dram)) {  in sdram_init_()
459 		if ((read_mr(dram, 1, 8) & 0x3) != 0x3)  in sdram_init_()
462 		if ((read_mr(dram, 1, 8) & 0x3) != 0x0)  in sdram_init_()
468 		if (data_training(dram, 1, sdram_params->base.dramtype) != 0) {  in sdram_init_()
472 		if (check_rd_gate(dram)) {  in sdram_init_()
479 		pctl_write_vrefdq(dram->pctl, 0x3, 5670,  in sdram_init_()
482 	dram_all_config(dram, sdram_params);  in sdram_init_()
483 	enable_low_power(dram, sdram_params);  in sdram_init_()
488 static int dram_detect_cap(struct dram_info *dram,  in dram_detect_cap()  argument
541 	if (data_training(dram, 1, dram_type) == 0)  in dram_detect_cap()
547 	dram_set_bw(dram, 2);  in dram_detect_cap()
548 	if (data_training(dram, 0, dram_type) == 0)  in dram_detect_cap()
597 static int sdram_init_detect(struct dram_info *dram,  in sdram_init_detect()  argument
605 	if (sdram_init_(dram, sdram_params, 0) != 0)  in sdram_init_detect()
608 	if (dram_detect_cap(dram, sdram_params, 0) != 0)  in sdram_init_detect()
614 	/* reinit sdram by real dram cap */  in sdram_init_detect()
615 	ret = sdram_init_(dram, sdram_params, 1);  in sdram_init_detect()
622 		sys_reg = readl(&dram->pmugrf->os_reg[2]);  in sdram_init_detect()
623 		sys_reg3 = readl(&dram->pmugrf->os_reg[3]);  in sdram_init_detect()
626 		writel(sys_reg, &dram->pmugrf->os_reg[2]);  in sdram_init_detect()
627 		writel(sys_reg3, &dram->pmugrf->os_reg[3]);  in sdram_init_detect()