Lines Matching +full:auto +full:- +full:detect
1 // SPDX-License-Identifier: GPL-2.0
55 #include "sdram-px30-lpddr3-detect-333.inc"
57 #include "sdram-px30-ddr3-detect-333.inc"
62 #include "sdram-px30-ddr_skew.inc"
71 &dram->cru->softrst_con[1]); in rkclk_ddr_reset()
73 &dram->cru->softrst_con[2]); in rkclk_ddr_reset()
104 writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode); in rkclk_set_dpll()
106 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); in rkclk_set_dpll()
108 &dram->cru->pll[1].con1); in rkclk_set_dpll()
112 if (LOCK(readl(&dram->cru->pll[1].con1))) in rkclk_set_dpll()
114 delay--; in rkclk_set_dpll()
117 writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode); in rkclk_set_dpll()
124 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHz * 2); in rkclk_configure_ddr()
128 * (-1), find ddrconfig fail
134 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in calculate_ddrconfig()
137 u32 ddrconf = -1; in calculate_ddrconfig()
139 bw = cap_info->bw; in calculate_ddrconfig()
140 die_bw = cap_info->dbw; in calculate_ddrconfig()
141 col = cap_info->col; in calculate_ddrconfig()
142 bank = cap_info->bk; in calculate_ddrconfig()
144 if (sdram_params->base.dramtype == DDR4) { in calculate_ddrconfig()
148 ddrconf = 12 - bw; in calculate_ddrconfig()
149 ddrconf = d4_rbc_2_d3_rbc[ddrconf - 7]; in calculate_ddrconfig()
151 tmp = ((bank - 2) << 3) | (col + bw - 10); in calculate_ddrconfig()
166 * argument sdram_params->ch.ddrconf must be right value before
172 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in set_ctl_address_map()
173 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map()
177 if (sdram_params->base.dramtype == DDR4) in set_ctl_address_map()
182 bg = (cap_info->dbw == 0) ? 2 : 1; in set_ctl_address_map()
186 cs_pst = cap_info->bw + cap_info->col + in set_ctl_address_map()
187 bg + cap_info->bk + cap_info->cs0_row; in set_ctl_address_map()
188 if (cs_pst >= 32 || cap_info->rank == 1) in set_ctl_address_map()
191 writel(cs_pst - 8, pctl_base + DDR_PCTL2_ADDRMAP0); in set_ctl_address_map()
193 ddrconf = cap_info->ddrconfig; in set_ctl_address_map()
194 if (sdram_params->base.dramtype == DDR4) { in set_ctl_address_map()
205 max_row = cs_pst - 1 - 8 - (addrmap[ddrconf][5] & 0xf); in set_ctl_address_map()
210 for (i = 17; i > max_row; i--) in set_ctl_address_map()
212 ((i - 12) * 8 / 32) * 4, in set_ctl_address_map()
213 0xf << ((i - 12) * 8 % 32), in set_ctl_address_map()
214 0xf << ((i - 12) * 8 % 32)); in set_ctl_address_map()
216 if ((sdram_params->base.dramtype == LPDDR3 || in set_ctl_address_map()
217 sdram_params->base.dramtype == LPDDR2) && in set_ctl_address_map()
218 cap_info->row_3_4) in set_ctl_address_map()
220 if (sdram_params->base.dramtype == DDR4 && cap_info->bw != 0x2) in set_ctl_address_map()
230 void __iomem *ddr_grf_base = dram->ddr_grf; in read_mr()
232 pctl_read_mr(dram->pctl, rank, mr_num); in read_mr()
241 void __iomem *phy_base = dram->phy; in check_rd_gate()
269 return -1; in check_rd_gate()
276 void __iomem *pctl_base = dram->pctl; in data_training()
281 /* disable auto low-power */ in data_training()
285 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training()
287 ret = phy_data_training(dram->phy, cs, dramtype); in data_training()
289 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training()
291 /* restore auto low-power */ in data_training()
299 phy_dram_set_bw(dram->phy, bw); in dram_set_bw()
304 writel(ddrconfig | (ddrconfig << 8), &dram->msch->deviceconf); in set_ddrconfig()
305 rk_clrsetreg(&dram->grf->soc_noc_con[1], 0x3 << 14, 0 << 14); in set_ddrconfig()
315 cs_cap[0] = sdram_get_cs_cap(cap_info, 0, base->dramtype); in sdram_msch_config()
316 cs_cap[1] = sdram_get_cs_cap(cap_info, 1, base->dramtype); in sdram_msch_config()
319 &msch->devicesize); in sdram_msch_config()
321 writel(noc_timings->ddrtiminga0.d32, in sdram_msch_config()
322 &msch->ddrtiminga0); in sdram_msch_config()
323 writel(noc_timings->ddrtimingb0.d32, in sdram_msch_config()
324 &msch->ddrtimingb0); in sdram_msch_config()
325 writel(noc_timings->ddrtimingc0.d32, in sdram_msch_config()
326 &msch->ddrtimingc0); in sdram_msch_config()
327 writel(noc_timings->devtodev0.d32, in sdram_msch_config()
328 &msch->devtodev0); in sdram_msch_config()
329 writel(noc_timings->ddrmode.d32, &msch->ddrmode); in sdram_msch_config()
330 writel(noc_timings->ddr4timing.d32, in sdram_msch_config()
331 &msch->ddr4timing); in sdram_msch_config()
332 writel(noc_timings->agingx0, &msch->agingx0); in sdram_msch_config()
333 writel(noc_timings->agingx0, &msch->aging0); in sdram_msch_config()
334 writel(noc_timings->agingx0, &msch->aging1); in sdram_msch_config()
335 writel(noc_timings->agingx0, &msch->aging2); in sdram_msch_config()
336 writel(noc_timings->agingx0, &msch->aging3); in sdram_msch_config()
342 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in dram_all_config()
346 set_ddrconfig(dram, cap_info->ddrconfig); in dram_all_config()
347 sdram_org_config(cap_info, &sdram_params->base, &sys_reg2, in dram_all_config()
349 writel(sys_reg2, &dram->pmugrf->os_reg[2]); in dram_all_config()
350 writel(sys_reg3, &dram->pmugrf->os_reg[3]); in dram_all_config()
351 sdram_msch_config(dram->msch, &sdram_params->ch.noc_timings, cap_info, in dram_all_config()
352 &sdram_params->base); in dram_all_config()
358 void __iomem *pctl_base = dram->pctl; in enable_low_power()
359 void __iomem *phy_base = dram->phy; in enable_low_power()
360 void __iomem *ddr_grf_base = dram->ddr_grf; in enable_low_power()
364 * bit0: grf_upctl_axi_cg_en = 1 enable upctl2 axi clk auto gating in enable_low_power()
366 * bit2: grf_upctl_core_cg_en = 1 enable upctl2 core clk auto gating in enable_low_power()
370 * bit8-11: grf_auto_sr_dly = 6 in enable_low_power()
372 writel(0x1f1f0617, &dram->ddr_grf->ddr_grf_con[1]); in enable_low_power()
374 if (sdram_params->base.dramtype == DDR4) in enable_low_power()
376 else if (sdram_params->base.dramtype == DDR3) in enable_low_power()
401 * pre_init: 0: pre init for dram cap detect
402 * 1: detect correct cap(except cs1 row)info, than reinit
403 * 2: after reinit, we detect cs1_row, if cs1_row not equal
410 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in sdram_init_()
411 void __iomem *pctl_base = dram->pctl; in sdram_init_()
426 phy_soft_reset(dram->phy); in sdram_init_()
429 pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE); in sdram_init_()
430 cap_info->ddrconfig = calculate_ddrconfig(sdram_params); in sdram_init_()
432 phy_cfg(dram->phy, &sdram_params->phy_regs, sdram_params->skew, in sdram_init_()
433 &sdram_params->base, cap_info->bw); in sdram_init_()
443 if (sdram_params->base.dramtype == LPDDR3) in sdram_init_()
444 pctl_write_mr(dram->pctl, 3, 11, 3, LPDDR3); in sdram_init_()
448 if (data_training(dram, 0, sdram_params->base.dramtype) != 0) { in sdram_init_()
451 return -1; in sdram_init_()
458 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init_()
460 return -1; in sdram_init_()
461 } else if (sdram_params->base.dramtype == LPDDR2) { in sdram_init_()
463 return -1; in sdram_init_()
466 if (pre_init != 0 && cap_info->rank == 2) { in sdram_init_()
468 if (data_training(dram, 1, sdram_params->base.dramtype) != 0) { in sdram_init_()
470 return -1; in sdram_init_()
478 if (sdram_params->base.dramtype == DDR4) in sdram_init_()
479 pctl_write_vrefdq(dram->pctl, 0x3, 5670, in sdram_init_()
480 sdram_params->base.dramtype); in sdram_init_()
492 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in dram_detect_cap()
505 u32 dram_type = sdram_params->base.dramtype; in dram_detect_cap()
508 /* detect col and bk for ddr3/lpddr3 */ in dram_detect_cap()
521 /* detect bg for ddr4 */ in dram_detect_cap()
528 cap_info->col = col; in dram_detect_cap()
529 cap_info->bk = bk; in dram_detect_cap()
533 /* detect row */ in dram_detect_cap()
537 /* detect row_3_4 */ in dram_detect_cap()
540 /* bw and cs detect using data training */ in dram_detect_cap()
545 cap_info->rank = cs + 1; in dram_detect_cap()
552 cap_info->bw = bw; in dram_detect_cap()
554 cap_info->cs0_high16bit_row = cap_info->cs0_row; in dram_detect_cap()
556 cap_info->cs1_row = cap_info->cs0_row; in dram_detect_cap()
557 cap_info->cs1_high16bit_row = cap_info->cs0_row; in dram_detect_cap()
559 cap_info->cs1_row = 0; in dram_detect_cap()
560 cap_info->cs1_high16bit_row = 0; in dram_detect_cap()
565 return -1; in dram_detect_cap()
571 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in get_ddr_param()
572 u32 dram_type = sdram_params->base.dramtype; in get_ddr_param()
578 if (cap_info->row_3_4) { in get_ddr_param()
583 if (cap_info->row_3_4 && cap_info->rank == 2) { in get_ddr_param()
584 ddr_param->count = 2; in get_ddr_param()
585 ddr_param->para[0] = 0; in get_ddr_param()
586 ddr_param->para[1] = cs_cap[0] * 4 / 3; in get_ddr_param()
587 ddr_param->para[2] = cs_cap[0]; in get_ddr_param()
588 ddr_param->para[3] = cs_cap[1]; in get_ddr_param()
590 ddr_param->count = 1; in get_ddr_param()
591 ddr_param->para[0] = 0; in get_ddr_param()
592 ddr_param->para[1] = (u64)cs_cap[0] + (u64)cs_cap[1]; in get_ddr_param()
600 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in sdram_init_detect()
606 return -1; in sdram_init_detect()
609 return -1; in sdram_init_detect()
612 pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info, in sdram_init_detect()
613 sdram_params->base.dramtype); in sdram_init_detect()
620 sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype); in sdram_init_detect()
621 if (cap_info->cs1_row) { in sdram_init_detect()
622 sys_reg = readl(&dram->pmugrf->os_reg[2]); in sdram_init_detect()
623 sys_reg3 = readl(&dram->pmugrf->os_reg[3]); in sdram_init_detect()
624 SYS_REG_ENC_CS1_ROW(cap_info->cs1_row, in sdram_init_detect()
626 writel(sys_reg, &dram->pmugrf->os_reg[2]); in sdram_init_detect()
627 writel(sys_reg3, &dram->pmugrf->os_reg[3]); in sdram_init_detect()
630 ret = sdram_detect_high_row(cap_info, sdram_params->base.dramtype); in sdram_init_detect()
667 sdram_print_ddr_info(&sdram_params->ch.cap_info, in sdram_init()
668 &sdram_params->base, 0); in sdram_init()
673 return (-1); in sdram_init()