19 	setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4);  in sdram_phy_dll_bypass_set()
20 	clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3);  in sdram_phy_dll_bypass_set()
21 	for (i = 0; i < 4; i++) {  in sdram_phy_dll_bypass_set()
22 		j = 0x26 + i * 0x10;  in sdram_phy_dll_bypass_set()
24 		clrbits_le32(PHY_REG(phy_base, j + 0x1), 1 << 3);  in sdram_phy_dll_bypass_set()
29 		setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f);  in sdram_phy_dll_bypass_set()
31 		clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f);  in sdram_phy_dll_bypass_set()
44 	for (i = 0; i < 4; i++) {  in sdram_phy_dll_bypass_set()
45 		j = 0x28 + i * 0x10;  in sdram_phy_dll_bypass_set()
71 	writel(cmd_drv, PHY_REG(phy_base, 0x11));  in sdram_phy_set_ds_odt()
72 	clrsetbits_le32(PHY_REG(phy_base, 0x12), 0x1f << 3, cmd_drv << 3);  in sdram_phy_set_ds_odt()
73 	writel(clk_drv, PHY_REG(phy_base, 0x16));  in sdram_phy_set_ds_odt()
74 	writel(clk_drv, PHY_REG(phy_base, 0x18));  in sdram_phy_set_ds_odt()
76 	for (i = 0; i < 4; i++) {  in sdram_phy_set_ds_odt()
77 		j = 0x20 + i * 0x10;  in sdram_phy_set_ds_odt()
79 		writel(dqs_drv, PHY_REG(phy_base, j + 0xf));  in sdram_phy_set_ds_odt()
81 		writel(dqs_odt, PHY_REG(phy_base, j + 0x1));  in sdram_phy_set_ds_odt()
82 		writel(dqs_odt, PHY_REG(phy_base, j + 0xe));  in sdram_phy_set_ds_odt()
88 	clrbits_le32(PHY_REG(phy_base, 0), 0x3 << 2);  in phy_soft_reset()
90 	setbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET);  in phy_soft_reset()
92 	setbits_le32(PHY_REG(phy_base, 0), DIGITAL_DERESET);  in phy_soft_reset()
99 		clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4);  in phy_dram_set_bw()
100 		setbits_le32(PHY_REG(phy_base, 0x46), 1 << 3);  in phy_dram_set_bw()
101 		setbits_le32(PHY_REG(phy_base, 0x56), 1 << 3);  in phy_dram_set_bw()
103 		clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4);  in phy_dram_set_bw()
104 		clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3);  in phy_dram_set_bw()
105 		clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3);  in phy_dram_set_bw()
106 	} else if (bw == 0) {  in phy_dram_set_bw()
107 		clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 1 << 4);  in phy_dram_set_bw()
108 		clrbits_le32(PHY_REG(phy_base, 0x36), 1 << 3);  in phy_dram_set_bw()
109 		clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3);  in phy_dram_set_bw()
110 		clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3);  in phy_dram_set_bw()
122 	odt_val = readl(PHY_REG(phy_base, 0x2e));  in phy_data_training()
124 	for (i = 0; i < 4; i++) {  in phy_data_training()
125 		j = 0x20 + i * 0x10;  in phy_data_training()
126 		writel(PHY_DDR3_RON_RTT_225ohm, PHY_REG(phy_base, j + 0x1));  in phy_data_training()
127 		writel(0, PHY_REG(phy_base, j + 0xe));  in phy_data_training()
131 		clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0);  in phy_data_training()
132 		clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0);  in phy_data_training()
133 		clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0);  in phy_data_training()
134 		clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0);  in phy_data_training()
137 	clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs));  in phy_data_training()
139 	clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1);  in phy_data_training()
141 	ret = readl(PHY_REG(phy_base, 0xff));  in phy_data_training()
143 	clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0);  in phy_data_training()
145 	clrbits_le32(PHY_REG(phy_base, 2), 0x30);  in phy_data_training()
149 		clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0x2);  in phy_data_training()
150 		clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0x2);  in phy_data_training()
151 		clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0x2);  in phy_data_training()
152 		clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0x2);  in phy_data_training()
155 	if (ret & 0x10) {  in phy_data_training()
158 		ret = (ret & 0xf) ^ (readl(PHY_REG(phy_base, 0)) >> 4);  in phy_data_training()
159 		ret = (ret == 0) ? 0 : -1;  in phy_data_training()
162 	for (i = 0; i < 4; i++) {  in phy_data_training()
163 		j = 0x20 + i * 0x10;  in phy_data_training()
164 		writel(odt_val, PHY_REG(phy_base, j + 0x1));  in phy_data_training()
165 		writel(odt_val, PHY_REG(phy_base, j + 0xe));  in phy_data_training()
177 	for (i = 0; phy_regs->phy[i][0] != 0xFFFFFFFF; i++) {  in phy_cfg()
179 		       phy_base + phy_regs->phy[i][0]);  in phy_cfg()
182 		clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4);  in phy_cfg()
184 		clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4);  in phy_cfg()
186 		clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3);  in phy_cfg()
187 		clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3);  in phy_cfg()
189 		clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 1 << 4);  in phy_cfg()
191 		clrbits_le32(PHY_REG(phy_base, 0x36), 1 << 3);  in phy_cfg()
192 		clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3);  in phy_cfg()
193 		clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3);  in phy_cfg()
199 	sdram_copy_to_reg(PHY_REG(phy_base, 0xb0),  in phy_cfg()
200 			  &skew->a0_a1_skew[0], 15 * 4);  in phy_cfg()
201 	sdram_copy_to_reg(PHY_REG(phy_base, 0x70),  in phy_cfg()
202 			  &skew->cs0_dm0_skew[0], 44 * 4);  in phy_cfg()
203 	sdram_copy_to_reg(PHY_REG(phy_base, 0xc0),  in phy_cfg()
204 			  &skew->cs1_dm0_skew[0], 44 * 4);  in phy_cfg()