532 				  struct rk3328_ddr_dts_config_timing *tim)  in rk3328_de_skew_setting_2_register()  argument
538 	memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew));  in rk3328_de_skew_setting_2_register()
539 	memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew));  in rk3328_de_skew_setting_2_register()
540 	memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew));  in rk3328_de_skew_setting_2_register()
548 		tim->ca_skew[offset] &= ~(0xf << shift);  in rk3328_de_skew_setting_2_register()
549 		tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift);  in rk3328_de_skew_setting_2_register()
561 		tim->cs0_skew[offset] &= ~(0xf << shift);  in rk3328_de_skew_setting_2_register()
562 		tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift);  in rk3328_de_skew_setting_2_register()
574 		tim->cs1_skew[offset] &= ~(0xf << shift);  in rk3328_de_skew_setting_2_register()
575 		tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift);  in rk3328_de_skew_setting_2_register()
580 				   struct px30_ddr_dts_config_timing *tim)  in px30_de_skew_set_2_reg()  argument
586 	memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew));  in px30_de_skew_set_2_reg()
587 	memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew));  in px30_de_skew_set_2_reg()
588 	memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew));  in px30_de_skew_set_2_reg()
596 		tim->ca_skew[offset] &= ~(0xf << shift);  in px30_de_skew_set_2_reg()
597 		tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift);  in px30_de_skew_set_2_reg()
609 		tim->cs0_skew[offset] &= ~(0xf << shift);  in px30_de_skew_set_2_reg()
610 		tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift);  in px30_de_skew_set_2_reg()
622 		tim->cs1_skew[offset] &= ~(0xf << shift);  in px30_de_skew_set_2_reg()
623 		tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift);  in px30_de_skew_set_2_reg()