30 	struct rk3368_ddr_pctl *pctl;  member
195 static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)  in send_command()  argument
200 	writel(mcmd, &pctl->mcmd);  in send_command()
201 	while (readl(&pctl->mcmd) & START_CMD)  in send_command()
205 static void send_mrs(struct rk3368_ddr_pctl *pctl,  in send_mrs()  argument
211 	writel(mcmd, &pctl->mcmd);  in send_mrs()
212 	while (readl(&pctl->mcmd) & START_CMD)  in send_mrs()
216 static int memory_init(struct rk3368_ddr_pctl *pctl,  in memory_init()  argument
228 	writel(POWER_UP_START, &pctl->powctl);  in memory_init()
237 	} while (!(readl(&pctl->powstat) & POWER_UP_DONE));  in memory_init()
251 	send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);  in memory_init()
253 	send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);  in memory_init()
254 	send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);  in memory_init()
255 	send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);  in memory_init()
256 	send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);  in memory_init()
257 	send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);  in memory_init()
258 	send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);  in memory_init()
263 static void move_to_config_state(struct rk3368_ddr_pctl *pctl)  in move_to_config_state()  argument
269 	u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;  in move_to_config_state()
273 		writel(WAKEUP_STATE, &pctl->sctl);  in move_to_config_state()
274 		while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)  in move_to_config_state()
280 		writel(CFG_STATE, &pctl->sctl);  in move_to_config_state()
281 		while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)  in move_to_config_state()
293 static void move_to_access_state(struct rk3368_ddr_pctl *pctl)  in move_to_access_state()  argument
299 	u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;  in move_to_access_state()
303 		if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &  in move_to_access_state()
307 		writel(WAKEUP_STATE, &pctl->sctl);  in move_to_access_state()
308 		while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)  in move_to_access_state()
313 		writel(CFG_STATE, &pctl->sctl);  in move_to_access_state()
314 		while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)  in move_to_access_state()
319 		writel(GO_STATE, &pctl->sctl);  in move_to_access_state()
320 		while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)  in move_to_access_state()
401 static int dfi_cfg(struct rk3368_ddr_pctl *pctl)  in dfi_cfg()  argument
406 	writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);  in dfi_cfg()
409 	       &pctl->dfistcfg1);  in dfi_cfg()
410 	writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);  in dfi_cfg()
412 	       &pctl->dfilpcfg0);  in dfi_cfg()
414 	writel(1, &pctl->dfitphyupdtype0);  in dfi_cfg()
416 	writel(0x1f, &pctl->dfitphyrdlat);  in dfi_cfg()
417 	writel(0, &pctl->dfitphywrdata);  in dfi_cfg()
418 	writel(0, &pctl->dfiupdcfg);  /* phyupd and ctrlupd disabled */  in dfi_cfg()
420 	setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);  in dfi_cfg()
429 	} while ((readl(&pctl->dfiststat0) & 1) == 0);  in dfi_cfg()
547 static void pctl_cfg(struct rk3368_ddr_pctl *pctl,  in pctl_cfg()  argument
553 	copy_to_reg(&pctl->togcnt1u, &params->pctl_timing.togcnt1u,  in pctl_cfg()
555 	writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);  in pctl_cfg()
558 	writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);  in pctl_cfg()
559 	writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);  in pctl_cfg()
562 	writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);  in pctl_cfg()
563 	writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);  in pctl_cfg()
566 	writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);  in pctl_cfg()
569 	setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);  in pctl_cfg()
572 static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,  in ddrphy_data_training()  argument
575 	const u32 trefi = readl(&pctl->trefi);  in ddrphy_data_training()
580 	writel(0 | BIT(31), &pctl->trefi);  in ddrphy_data_training()
594 	send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);  in ddrphy_data_training()
597 	writel(trefi | BIT(31), &pctl->trefi);  in ddrphy_data_training()
606 	struct rk3368_ddr_pctl *pctl = priv->pctl;  in sdram_col_row_detect()  local
612 	move_to_config_state(pctl);  in sdram_col_row_detect()
614 	move_to_access_state(pctl);  in sdram_col_row_detect()
632 	move_to_config_state(pctl);  in sdram_col_row_detect()
634 	move_to_access_state(pctl);  in sdram_col_row_detect()
801 	struct rk3368_ddr_pctl *pctl = priv->pctl;  in setup_sdram()  local
823 	dfi_cfg(pctl);  in setup_sdram()
830 	pctl_cfg(pctl, params, grf);  in setup_sdram()
838 	ret = memory_init(pctl, params);  in setup_sdram()
842 	move_to_config_state(pctl);  in setup_sdram()
844 	ddrphy_data_training(pctl, ddrphy);  in setup_sdram()
845 	move_to_access_state(pctl);  in setup_sdram()
913 	struct rk3368_ddr_pctl *pctl;  in rk3368_dmc_probe()  local
933 	pctl = (struct rk3368_ddr_pctl *)plat->of_plat.reg[0];  in rk3368_dmc_probe()
938 	priv->pctl = pctl;  in rk3368_dmc_probe()