122 void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val);
252 	uec_phy_write(mii_info, MII_ADVERTISE, adv);  in config_genmii_advert()
290 	uec_phy_write(mii_info, MII_BMCR, ctrl);  in genmii_setup_forced()
300 	uec_phy_write(mii_info, MII_BMCR, ctl);  in genmii_restart_aneg()
320 		uec_phy_write(mii_info, MII_CTRL1000, adv);  in gbit_config_aneg()
335 	uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);  in marvell_config_aneg()
337 	uec_phy_write(mii_info, 0x1d, 0x1f);  in marvell_config_aneg()
338 	uec_phy_write(mii_info, 0x1e, 0x200c);  in marvell_config_aneg()
339 	uec_phy_write(mii_info, 0x1d, 0x5);  in marvell_config_aneg()
340 	uec_phy_write(mii_info, 0x1e, 0);  in marvell_config_aneg()
341 	uec_phy_write(mii_info, 0x1e, 0x100);  in marvell_config_aneg()
468 		uec_phy_write(mii_info, 0x18, 0x7 | (7 << 12));  in bcm_init()
476 		uec_phy_write(mii_info, 0x18, val);  in bcm_init()
505 		uec_phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);  in uec_marvell_init()
510 		uec_phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);  in uec_marvell_init()
512 		uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);  in uec_marvell_init()
573 		uec_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);  in marvell_config_intr()
575 		uec_phy_write(mii_info, MII_M1011_IMASK,  in marvell_config_intr()
584 	uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) |  in dm9161_init()
587 	uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) &  in dm9161_init()
590 	uec_phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);  in dm9161_init()
642 		uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);  in dm9161_config_intr()
644 		uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);  in dm9161_config_intr()
811 void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)  in uec_phy_write()  function
869 			uec_phy_write(mii_info, 0x00, 0x9140);  in marvell_phy_interface_mode()
870 			uec_phy_write(mii_info, 0x1d, 0x001f);  in marvell_phy_interface_mode()
871 			uec_phy_write(mii_info, 0x1e, 0x200c);  in marvell_phy_interface_mode()
872 			uec_phy_write(mii_info, 0x1d, 0x0005);  in marvell_phy_interface_mode()
873 			uec_phy_write(mii_info, 0x1e, 0x0000);  in marvell_phy_interface_mode()
874 			uec_phy_write(mii_info, 0x1e, 0x0100);  in marvell_phy_interface_mode()
875 			uec_phy_write(mii_info, 0x09, 0x0e00);  in marvell_phy_interface_mode()
876 			uec_phy_write(mii_info, 0x04, 0x01e1);  in marvell_phy_interface_mode()
877 			uec_phy_write(mii_info, 0x00, 0x9140);  in marvell_phy_interface_mode()
878 			uec_phy_write(mii_info, 0x00, 0x1000);  in marvell_phy_interface_mode()
880 			uec_phy_write(mii_info, 0x00, 0x2900);  in marvell_phy_interface_mode()
881 			uec_phy_write(mii_info, 0x14, 0x0cd2);  in marvell_phy_interface_mode()
882 			uec_phy_write(mii_info, 0x00, 0xa100);  in marvell_phy_interface_mode()
883 			uec_phy_write(mii_info, 0x09, 0x0000);  in marvell_phy_interface_mode()
884 			uec_phy_write(mii_info, 0x1b, 0x800b);  in marvell_phy_interface_mode()
885 			uec_phy_write(mii_info, 0x04, 0x05e1);  in marvell_phy_interface_mode()
886 			uec_phy_write(mii_info, 0x00, 0xa100);  in marvell_phy_interface_mode()
887 			uec_phy_write(mii_info, 0x00, 0x2100);  in marvell_phy_interface_mode()
890 			uec_phy_write(mii_info, 0x14, 0x8e40);  in marvell_phy_interface_mode()
891 			uec_phy_write(mii_info, 0x1b, 0x800b);  in marvell_phy_interface_mode()
892 			uec_phy_write(mii_info, 0x14, 0x0c82);  in marvell_phy_interface_mode()
893 			uec_phy_write(mii_info, 0x00, 0x8100);  in marvell_phy_interface_mode()
901 		uec_phy_write(mii_info, MII_BMCR, status | BMCR_ANENABLE);  in marvell_phy_interface_mode()