27 qe_map_t		*qe_immr = NULL;  variable
39 		out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));  in qe_issue_cmd()
41 		out_be32(&qe_immr->cp.cecdr, cmd_data);  in qe_issue_cmd()
42 		out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |  in qe_issue_cmd()
47 		cecr = in_be32(&qe_immr->cp.cecr);  in qe_issue_cmd()
78 	memset((void *)&qe_immr->muram[retloc], 0, size);  in qe_muram_alloc()
88 	return (void *)&qe_immr->muram[offset];  in qe_muram_addr()
97 	p = (volatile sdma_t *)&qe_immr->sdma;  in qe_sdma_init()
177 	qe_immr = (qe_map_t *)qe_base;  in qe_init()
186 	out_be32(&qe_immr->iram.iready,QE_IRAM_READY);  in qe_init()
200 	qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);  in u_qe_init()
227 	out_be32(&qe_immr->iram.iready, QE_IRAM_READY);  in u_qe_init()
256 	out_be32(&qe_immr->cp.cecdr, para_ram_base);  in qe_assign_page()
257 	out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)  in qe_assign_page()
262 		cecr = in_be32(&qe_immr->cp.cecr);  in qe_assign_page()
288 	bp = (uint *)&qe_immr->brg.brgc1;  in qe_set_brg()
321 	cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);  in qe_set_mii_clk_src()
324 	out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);  in qe_set_mii_clk_src()
358 	out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |  in qe_upload_microcode()
362 		out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));  in qe_upload_microcode()
458 		out_be16(&qe_immr->cp.cercr,  in qe_upload_firmware()
459 			in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);  in qe_upload_firmware()
493 				out_be32(&qe_immr->rsp[i].tibcr[j], trap);  in qe_upload_firmware()
497 		out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));  in qe_upload_firmware()
597 		out_be16(&qe_immr->cp.cercr,  in u_qe_upload_firmware()
598 			 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);  in u_qe_upload_firmware()
621 				out_be32(&qe_immr->rsp[i].tibcr[j], trap);  in u_qe_upload_firmware()
625 		out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));  in u_qe_upload_firmware()