4  * SPDX-License-Identifier:     GPL-2.0+
21 static int exynos_pwm_set_config(struct udevice *dev, uint channel,  in exynos_pwm_set_config()  argument
25 	struct s5p_timer *regs = priv->regs;  in exynos_pwm_set_config()
29 	u32 tcnt, tcmp, tcon;  in exynos_pwm_set_config()  local
31 	if (channel >= 5)  in exynos_pwm_set_config()
32 		return -EINVAL;  in exynos_pwm_set_config()
33 	debug("%s: Configure '%s' channel %u, period_ns %u, duty_ns %u\n",  in exynos_pwm_set_config()
34 	      __func__, dev->name, channel, period_ns, duty_ns);  in exynos_pwm_set_config()
36 	val = readl(&regs->tcfg0);  in exynos_pwm_set_config()
37 	prescaler = (channel < 2 ? val : (val >> 8)) & 0xff;  in exynos_pwm_set_config()
38 	div = (readl(&regs->tcfg1) >> MUX_DIV_SHIFT(channel)) & 0xf;  in exynos_pwm_set_config()
43 	if (channel < 4) {  in exynos_pwm_set_config()
48 		offset = channel * 3;  in exynos_pwm_set_config()
49 		writel(tcnt, &regs->tcntb0 + offset);  in exynos_pwm_set_config()
50 		writel(tcmp, &regs->tcmpb0 + offset);  in exynos_pwm_set_config()
53 	tcon = readl(&regs->tcon);  in exynos_pwm_set_config()
54 	tcon |= TCON_UPDATE(channel);  in exynos_pwm_set_config()
55 	if (channel < 4)  in exynos_pwm_set_config()
56 		tcon |= TCON_AUTO_RELOAD(channel);  in exynos_pwm_set_config()
58 		tcon |= TCON4_AUTO_RELOAD;  in exynos_pwm_set_config()
59 	writel(tcon, &regs->tcon);  in exynos_pwm_set_config()
61 	tcon &= ~TCON_UPDATE(channel);  in exynos_pwm_set_config()
62 	writel(tcon, &regs->tcon);  in exynos_pwm_set_config()
67 static int exynos_pwm_set_enable(struct udevice *dev, uint channel,  in exynos_pwm_set_enable()  argument
71 	struct s5p_timer *regs = priv->regs;  in exynos_pwm_set_enable()
74 	if (channel >= 4)  in exynos_pwm_set_enable()
75 		return -EINVAL;  in exynos_pwm_set_enable()
76 	debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel);  in exynos_pwm_set_enable()
77 	mask = TCON_START(channel);  in exynos_pwm_set_enable()
78 	clrsetbits_le32(&regs->tcon, mask, enable ? mask : 0);  in exynos_pwm_set_enable()
86 	struct s5p_timer *regs = priv->regs;  in exynos_pwm_probe()
88 	writel(PRESCALER_0 | PRESCALER_1 << 8, &regs->tcfg0);  in exynos_pwm_probe()
97 	priv->regs = (struct s5p_timer *)devfdt_get_addr(dev);  in exynos_pwm_ofdata_to_platdata()
108 	{ .compatible = "samsung,exynos4210-pwm" },