Lines Matching +full:buck +full:- +full:boost
6 * SPDX-License-Identifier: GPL-2.0+
19 * struct pfuze100_regulator_desc - regulator descriptor
44 * struct pfuze100_regulator_platdata - platform data for pfuze100
149 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000, -1
153 -1, -1, -1, -1, -1, -1, 3000000, -1
219 /* SWx Buck regulator mode */
232 /* Boost Buck regulator mode for normal operation */
253 if (!strcmp(desc->name, name)) in se_desc()
271 dev->name); in pfuze100_regulator_probe()
276 dev->name); in pfuze100_regulator_probe()
281 dev->name); in pfuze100_regulator_probe()
285 return -EINVAL; in pfuze100_regulator_probe()
288 debug("Do not support regulator %s\n", dev->name); in pfuze100_regulator_probe()
289 return -EINVAL; in pfuze100_regulator_probe()
292 plat->desc = desc; in pfuze100_regulator_probe()
295 uc_pdata->type = desc->type; in pfuze100_regulator_probe()
296 if (uc_pdata->type == REGULATOR_TYPE_BUCK) { in pfuze100_regulator_probe()
297 if (!strcmp(dev->name, "swbst")) { in pfuze100_regulator_probe()
298 uc_pdata->mode = pfuze_swbst_modes; in pfuze100_regulator_probe()
299 uc_pdata->mode_count = ARRAY_SIZE(pfuze_swbst_modes); in pfuze100_regulator_probe()
301 uc_pdata->mode = pfuze_sw_modes; in pfuze100_regulator_probe()
302 uc_pdata->mode_count = ARRAY_SIZE(pfuze_sw_modes); in pfuze100_regulator_probe()
304 } else if (uc_pdata->type == REGULATOR_TYPE_LDO) { in pfuze100_regulator_probe()
305 uc_pdata->mode = pfuze_ldo_modes; in pfuze100_regulator_probe()
306 uc_pdata->mode_count = ARRAY_SIZE(pfuze_ldo_modes); in pfuze100_regulator_probe()
308 uc_pdata->mode = NULL; in pfuze100_regulator_probe()
309 uc_pdata->mode_count = 0; in pfuze100_regulator_probe()
319 struct pfuze100_regulator_desc *desc = plat->desc; in pfuze100_regulator_mode()
322 if (desc->type == REGULATOR_TYPE_BUCK) { in pfuze100_regulator_mode()
323 if (!strcmp(dev->name, "swbst")) { in pfuze100_regulator_mode()
324 val = pmic_reg_read(dev->parent, in pfuze100_regulator_mode()
325 desc->vsel_reg); in pfuze100_regulator_mode()
335 val = pmic_reg_read(dev->parent, in pfuze100_regulator_mode()
336 desc->vsel_reg + in pfuze100_regulator_mode()
347 } else if (desc->type == REGULATOR_TYPE_LDO) { in pfuze100_regulator_mode()
348 val = pmic_reg_read(dev->parent, desc->vsel_reg); in pfuze100_regulator_mode()
358 return -EINVAL; in pfuze100_regulator_mode()
362 if (desc->type == REGULATOR_TYPE_BUCK) { in pfuze100_regulator_mode()
363 if (!strcmp(dev->name, "swbst")) in pfuze100_regulator_mode()
364 return pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_mode()
368 val = pmic_clrsetbits(dev->parent, in pfuze100_regulator_mode()
369 desc->vsel_reg + PFUZE100_MODE_OFFSET, in pfuze100_regulator_mode()
373 } else if (desc->type == REGULATOR_TYPE_LDO) { in pfuze100_regulator_mode()
374 val = pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_mode()
379 return -EINVAL; in pfuze100_regulator_mode()
393 if (!strcmp(dev->name, "vrefddr")) { in pfuze100_regulator_enable()
394 val = pmic_reg_read(dev->parent, PFUZE100_VREFDDRCON); in pfuze100_regulator_enable()
417 if (!strcmp(dev->name, "vrefddr")) { in pfuze100_regulator_enable()
418 val = pmic_reg_read(dev->parent, PFUZE100_VREFDDRCON); in pfuze100_regulator_enable()
426 return pmic_reg_write(dev->parent, PFUZE100_VREFDDRCON, in pfuze100_regulator_enable()
430 if (uc_pdata->type == REGULATOR_TYPE_LDO) { in pfuze100_regulator_enable()
432 } else if (uc_pdata->type == REGULATOR_TYPE_BUCK) { in pfuze100_regulator_enable()
433 if (!strcmp(dev->name, "swbst")) in pfuze100_regulator_enable()
439 return -EINVAL; in pfuze100_regulator_enable()
453 struct pfuze100_regulator_desc *desc = plat->desc; in pfuze100_regulator_val()
459 if (uc_pdata->type == REGULATOR_TYPE_FIXED) { in pfuze100_regulator_val()
460 *uV = desc->voltage; in pfuze100_regulator_val()
461 } else if (desc->volt_table) { in pfuze100_regulator_val()
462 val = pmic_reg_read(dev->parent, desc->vsel_reg); in pfuze100_regulator_val()
465 val &= desc->vsel_mask; in pfuze100_regulator_val()
466 *uV = desc->volt_table[val]; in pfuze100_regulator_val()
468 if (uc_pdata->min_uV < 0) { in pfuze100_regulator_val()
470 return -EINVAL; in pfuze100_regulator_val()
472 val = pmic_reg_read(dev->parent, desc->vsel_reg); in pfuze100_regulator_val()
475 val &= desc->vsel_mask; in pfuze100_regulator_val()
476 *uV = uc_pdata->min_uV + (int)val * desc->uV_step; in pfuze100_regulator_val()
482 if (uc_pdata->type == REGULATOR_TYPE_FIXED) { in pfuze100_regulator_val()
484 return -EINVAL; in pfuze100_regulator_val()
485 } else if (desc->volt_table) { in pfuze100_regulator_val()
486 for (i = 0; i < desc->vsel_mask; i++) { in pfuze100_regulator_val()
487 if (*uV == desc->volt_table[i]) in pfuze100_regulator_val()
490 if (i == desc->vsel_mask) { in pfuze100_regulator_val()
492 return -EINVAL; in pfuze100_regulator_val()
495 return pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_val()
496 desc->vsel_mask, i); in pfuze100_regulator_val()
498 if (uc_pdata->min_uV < 0) { in pfuze100_regulator_val()
500 return -EINVAL; in pfuze100_regulator_val()
502 return pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_val()
503 desc->vsel_mask, in pfuze100_regulator_val()
504 (*uV - uc_pdata->min_uV) / desc->uV_step); in pfuze100_regulator_val()