18 #define RK_FUNC_GPIO			0
42 #define IOMUX_GPIO_ONLY		BIT(0)
69 	DRV_TYPE_IO_DEFAULT = 0,
85 	PULL_TYPE_IO_DEFAULT = 0,
98 	ROUTE_TYPE_DEFAULT = 0,
222 		.pull_type[0] = pull0,					\
270 		.pull_type[0] = pull0,					\
298 		.pull_type[0] = pull0,					\
417 	return 0;  in rockchip_verify_config()
423 		.pin = 0,
424 		.reg = 0x418,
425 		.bit = 0,
426 		.mask = 0x3
430 		.reg = 0x418,
432 		.mask = 0x3
436 		.reg = 0x418,
438 		.mask = 0x3
442 		.reg = 0x418,
444 		.mask = 0x3
448 		.reg = 0x418,
450 		.mask = 0x3
454 		.reg = 0x418,
456 		.mask = 0x3
460 		.reg = 0x418,
462 		.mask = 0x3
466 		.reg = 0x418,
468 		.mask = 0x3
472 		.reg = 0x41c,
473 		.bit = 0,
474 		.mask = 0x3
478 		.reg = 0x41c,
480 		.mask = 0x3
486 		.num = 0,
488 		.reg = 0x10000,
489 		.bit = 0,
490 		.mask = 0xf
493 		.num = 0,
495 		.reg = 0x10000,
497 		.mask = 0xf
500 		.num = 0,
502 		.reg = 0x10000,
504 		.mask = 0xf
507 		.num = 0,
509 		.reg = 0x10000,
511 		.mask = 0xf
519 		.reg = 0xe8,
520 		.bit = 0,
521 		.mask = 0x7
525 		.reg = 0xe8,
527 		.mask = 0x7
531 		.reg = 0xe8,
533 		.mask = 0x7
537 		.reg = 0xe8,
539 		.mask = 0x7
543 		.reg = 0xd4,
545 		.mask = 0x7
553 		.reg = 0x28,
555 		.mask = 0x7
559 		.reg = 0x2c,
560 		.bit = 0,
561 		.mask = 0x3
565 		.reg = 0x30,
567 		.mask = 0x7
571 		.reg = 0x30,
573 		.mask = 0x7
577 		.reg = 0x30,
579 		.mask = 0x7
583 		.reg = 0x34,
584 		.bit = 0,
585 		.mask = 0x7
589 		.reg = 0x34,
591 		.mask = 0x7
595 		.reg = 0x34,
597 		.mask = 0x7
601 		.reg = 0x68,
603 		.mask = 0x7
607 		.reg = 0x68,
609 		.mask = 0x7
617 		.reg = 0x28,
619 		.mask = 0xf
623 		.reg = 0x2c,
624 		.bit = 0,
625 		.mask = 0x3
629 		.reg = 0x30,
631 		.mask = 0xf
635 		.reg = 0x30,
637 		.mask = 0xf
641 		.reg = 0x30,
643 		.mask = 0xf
647 		.reg = 0x34,
648 		.bit = 0,
649 		.mask = 0xf
653 		.reg = 0x34,
655 		.mask = 0xf
659 		.reg = 0x34,
661 		.mask = 0xf
665 		.reg = 0x68,
667 		.mask = 0xf
671 		.reg = 0x68,
673 		.mask = 0xf
677 		.reg = 0x608,
678 		.bit = 0,
679 		.mask = 0x7
683 		.reg = 0x608,
685 		.mask = 0x7
689 		.reg = 0x610,
691 		.mask = 0x7
695 		.reg = 0x610,
696 		.bit = 0,
697 		.mask = 0x7
701 		.reg = 0x610,
703 		.mask = 0x7
711 		.reg = 0x24,
713 		.mask = 0x3
717 		.reg = 0x28,
718 		.bit = 0,
719 		.mask = 0x7
723 		.reg = 0x30,
725 		.mask = 0x3
730 	MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
731 	MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
733 	MR_TOPGRF(RK_GPIO0, RK_PD4, RK_FUNC_4, 0x10260, RK_GENMASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
734 	MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
735 	MR_TOPGRF(RK_GPIO2, RK_PC7, RK_FUNC_6, 0x10260, RK_GENMASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
737 	MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
738 	MR_TOPGRF(RK_GPIO2, RK_PB3, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
740 	MR_TOPGRF(RK_GPIO3, RK_PD4, RK_FUNC_2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
741 	MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
743 	MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
744 	MR_TOPGRF(RK_GPIO2, RK_PD1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
746 	MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
747 	MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
748 	MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
750 	MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
751 	MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
753 	MR_TOPGRF(RK_GPIO2, RK_PA5, RK_FUNC_7, 0x10264, RK_GENMASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
754 	MR_TOPGRF(RK_GPIO3, RK_PB0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
755 	MR_TOPGRF(RK_GPIO1, RK_PD0, RK_FUNC_4, 0x10264, RK_GENMASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
757 	MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
758 	MR_TOPGRF(RK_GPIO1, RK_PC6, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
759 	MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_6, 0x10264, RK_GENMASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
761 	MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
762 	MR_TOPGRF(RK_GPIO2, RK_PB7, RK_FUNC_2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
764 	MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
765 	MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
767 	MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */
768 	MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */
770 	MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */
771 	MR_TOPGRF(RK_GPIO2, RK_PD6, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */
773 	MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */
774 	MR_TOPGRF(RK_GPIO2, RK_PD5, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */
776 	MR_TOPGRF(RK_GPIO3, RK_PA7, RK_FUNC_6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
777 	MR_TOPGRF(RK_GPIO3, RK_PA1, RK_FUNC_5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
779 	MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
780 	MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
782 	MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
783 	MR_TOPGRF(RK_GPIO1, RK_PA7, RK_FUNC_2, 0x10268, RK_GENMASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
784 	MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
786 	MR_TOPGRF(RK_GPIO3, RK_PA4, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
787 	MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
788 	MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
790 	MR_TOPGRF(RK_GPIO3, RK_PA6, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
791 	MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_4, 0x10268, RK_GENMASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
792 	MR_TOPGRF(RK_GPIO2, RK_PA0, RK_FUNC_3, 0x10268, RK_GENMASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
794 	MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(0, 0, 0)), /* PWM0_M0 */
795 	MR_PMUGRF(RK_GPIO2, RK_PB3, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(0, 0, 1)), /* PWM0_M1 */
797 	MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(2, 2, 0)), /* PWM1_M0 */
798 	MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(2, 2, 1)), /* PWM1_M1 */
800 	MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(4, 4, 0)), /* PWM2_M0 */
801 	MR_PMUGRF(RK_GPIO2, RK_PB1, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(4, 4, 1)), /* PWM2_M1 */
803 	MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
804 	MR_PMUGRF(RK_GPIO2, RK_PB0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
806 	MR_PMUGRF(RK_GPIO0, RK_PC2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(8, 8, 0)), /* PWM4_M0 */
807 	MR_PMUGRF(RK_GPIO2, RK_PA7, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(8, 8, 1)), /* PWM4_M1 */
809 	MR_PMUGRF(RK_GPIO0, RK_PC3, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(10, 10, 0)), /* PWM5_M0 */
810 	MR_PMUGRF(RK_GPIO2, RK_PA6, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(10, 10, 1)), /* PWM5_M1 */
812 	MR_PMUGRF(RK_GPIO0, RK_PB2, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(12, 12, 0)), /* PWM6_M0 */
813 	MR_PMUGRF(RK_GPIO2, RK_PD4, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(12, 12, 1)), /* PWM6_M1 */
815 	MR_PMUGRF(RK_GPIO0, RK_PB1, RK_FUNC_3, 0x0114, RK_GENMASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
816 	MR_PMUGRF(RK_GPIO3, RK_PA0, RK_FUNC_5, 0x0114, RK_GENMASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
818 	MR_PMUGRF(RK_GPIO0, RK_PB0, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
819 	MR_PMUGRF(RK_GPIO2, RK_PA1, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
820 	MR_PMUGRF(RK_GPIO2, RK_PB2, RK_FUNC_6, 0x0118, RK_GENMASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
822 	MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_2, 0x0118, RK_GENMASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
823 	MR_PMUGRF(RK_GPIO1, RK_PD0, RK_FUNC_5, 0x0118, RK_GENMASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
824 	MR_PMUGRF(RK_GPIO0, RK_PC3, RK_FUNC_1, 0x0118, RK_GENMASK_VAL(4, 4, 1)), /* I2C2 */
835 	for (i = 0; i < ctrl->niomux_recalced; i++) {  in rockchip_get_recalced_mux()
854 		.pin = 0,
856 		.route_offset = 0x184,
863 		.route_offset = 0x184,
870 		.route_offset = 0x184,
877 		.route_offset = 0x184,
884 		.route_offset = 0x184,
891 		.route_offset = 0x184,
895 		.bank_num = 0,
898 		.route_offset = 0x184,
905 		.route_offset = 0x184,
916 		.route_offset = 0x190,
923 		.route_offset = 0x190,
930 		.route_offset = 0x190,
937 		.route_offset = 0x190,
944 		.route_offset = 0x190,
951 		/* spi-0 */
955 		.route_offset = 0x144,
962 		.route_offset = 0x144,
966 		.bank_num = 0,
969 		.route_offset = 0x144,
972 		/* i2s-0 */
976 		.route_offset = 0x144,
980 		.bank_num = 0,
983 		.route_offset = 0x144,
986 		/* emmc-0 */
990 		.route_offset = 0x144,
997 		.route_offset = 0x144,
1004 		/* pwm0-0 */
1005 		.bank_num = 0,
1008 		.route_offset = 0x50,
1015 		.route_offset = 0x50,
1016 		.route_val = BIT(16) | BIT(0),
1018 		/* pwm1-0 */
1019 		.bank_num = 0,
1022 		.route_offset = 0x50,
1026 		.bank_num = 0,
1029 		.route_offset = 0x50,
1032 		/* pwm2-0 */
1033 		.bank_num = 0,
1036 		.route_offset = 0x50,
1043 		.route_offset = 0x50,
1046 		/* pwm3-0 */
1050 		.route_offset = 0x50,
1057 		.route_offset = 0x50,
1060 		/* sdio-0_d0 */
1064 		.route_offset = 0x50,
1071 		.route_offset = 0x50,
1074 		/* spi-0_rx */
1075 		.bank_num = 0,
1078 		.route_offset = 0x50,
1083 		.pin = 0,
1085 		.route_offset = 0x50,
1088 		/* emmc-0_cmd */
1092 		.route_offset = 0x50,
1099 		.route_offset = 0x50,
1102 		/* uart2-0_rx */
1106 		.route_offset = 0x50,
1113 		.route_offset = 0x50,
1116 		/* uart1-0_rx */
1120 		.route_offset = 0x50,
1127 		.route_offset = 0x50,
1138 		.route_offset = 0x264,
1145 		.route_offset = 0x264,
1153 		.bank_num = 0,
1156 		.route_offset = 0x314,
1157 		.route_val = BIT(16 + 0) | BIT(0),
1163 		.route_offset = 0x314,
1170 		.route_offset = 0x314,
1174 		.bank_num = 0,
1177 		.route_offset = 0x314,
1184 		.route_offset = 0x314,
1191 		.route_offset = 0x308,
1198 		.route_offset = 0x308,
1205 		.route_offset = 0x308,
1212 		.route_offset = 0x308,
1219 		.route_offset = 0x308,
1226 		.route_offset = 0x308,
1233 		.route_offset = 0x308,
1240 		.route_offset = 0x600,
1248 		.bank_num = 0,
1251 		.route_offset = 0x314,
1252 		.route_val = BIT(16 + 0) | BIT(0),
1258 		.route_offset = 0x314,
1265 		.route_offset = 0x314,
1269 		.bank_num = 0,
1272 		.route_offset = 0x608,
1279 		.route_offset = 0x608,
1284 		.pin = 0,
1286 		.route_offset = 0x608,
1293 		.route_offset = 0x308,
1300 		.route_offset = 0x308,
1307 		.route_offset = 0x308,
1314 		.route_offset = 0x308,
1321 		.route_offset = 0x308,
1328 		.route_offset = 0x308,
1335 		.route_offset = 0x308,
1342 		.route_offset = 0x600,
1349 		.route_offset = 0x314,
1356 		.route_offset = 0x314,
1360 		.bank_num = 0,
1363 		.route_offset = 0x314,
1370 		.route_offset = 0x314,
1377 		.route_offset = 0x314,
1381 		.bank_num = 0,
1384 		.route_offset = 0x314,
1391 		.route_offset = 0x314,
1398 		.route_offset = 0x314,
1405 		.route_offset = 0x314,
1412 		.route_offset = 0x314,
1419 		.route_offset = 0x314,
1423 		.bank_num = 0,
1426 		.route_offset = 0x314,
1437 		.route_offset = 0x50,
1444 		.route_offset = 0x50,
1445 		.route_val = BIT(16) | BIT(16 + 1) | BIT(0),
1451 		.route_offset = 0x50,
1458 		.route_offset = 0x50,
1465 		.route_offset = 0x50,
1472 		.route_offset = 0x50,
1479 		.route_offset = 0x50,
1486 		.route_offset = 0x50,
1493 		.route_offset = 0x50,
1500 		.route_offset = 0x50,
1507 		.route_offset = 0x50,
1514 		.route_offset = 0x50,
1525 		.route_offset = 0xe21c,
1532 		.route_offset = 0xe21c,
1539 		.route_offset = 0xe21c,
1546 		.route_offset = 0xe21c,
1553 		.route_offset = 0xe21c,
1567 	for (i = 0; i < ctrl->niomux_routes; i++) {  in rockchip_get_mux_route()
1615 			reg += 0x4;  in rockchip_get_mux()
1617 		mask = 0xf;  in rockchip_get_mux()
1620 			reg += 0x4;  in rockchip_get_mux()
1622 		mask = 0x7;  in rockchip_get_mux()
1625 		mask = 0x3;  in rockchip_get_mux()
1666 	return 0;  in rockchip_verify_mux()
1692 	if (ret < 0)  in rockchip_set_mux()
1696 		return 0;  in rockchip_set_mux()
1712 			reg += 0x4;  in rockchip_set_mux()
1714 		mask = 0xf;  in rockchip_set_mux()
1717 			reg += 0x4;  in rockchip_set_mux()
1719 		mask = 0x7;  in rockchip_set_mux()
1722 		mask = 0x3;  in rockchip_set_mux()
1729 		u32 route_reg = 0, route_val = 0;  in rockchip_set_mux()
1762 #define PX30_PULL_PMU_OFFSET		0x10
1763 #define PX30_PULL_GRF_OFFSET		0x60
1775 	if (bank->bank_num == 0) {  in px30_calc_pull_reg_and_bit()
1783 		*reg -= 0x10;  in px30_calc_pull_reg_and_bit()
1792 #define PX30_DRV_PMU_OFFSET		0x20
1793 #define PX30_DRV_GRF_OFFSET		0xf0
1805 	if (bank->bank_num == 0) {  in px30_calc_drv_reg_and_bit()
1813 		*reg -= 0x10;  in px30_calc_drv_reg_and_bit()
1822 #define PX30_SCHMITT_PMU_OFFSET			0x38
1823 #define PX30_SCHMITT_GRF_OFFSET			0xc0
1836 	if (bank->bank_num == 0) {  in px30_calc_schmitt_reg_and_bit()
1849 	return 0;  in px30_calc_schmitt_reg_and_bit()
1852 #define RV1108_PULL_PMU_OFFSET		0x10
1853 #define RV1108_PULL_OFFSET		0x110
1865 	if (bank->bank_num == 0) {  in rv1108_calc_pull_reg_and_bit()
1872 		*reg -= 0x10;  in rv1108_calc_pull_reg_and_bit()
1881 #define RV1108_DRV_PMU_OFFSET		0x20
1882 #define RV1108_DRV_GRF_OFFSET		0x210
1894 	if (bank->bank_num == 0) {  in rv1108_calc_drv_reg_and_bit()
1902 		*reg -= 0x10;  in rv1108_calc_drv_reg_and_bit()
1911 #define RV1108_SCHMITT_PMU_OFFSET		0x30
1912 #define RV1108_SCHMITT_GRF_OFFSET		0x388
1925 	if (bank->bank_num == 0) {  in rv1108_calc_schmitt_reg_and_bit()
1938 	return 0;  in rv1108_calc_schmitt_reg_and_bit()
1941 #define RV1126_PULL_PMU_OFFSET		0x40
1942 #define RV1126_PULL_GRF_GPIO1A0_OFFSET		0x10108
1955 	if (bank->bank_num == 0) {  in rv1126_calc_pull_reg_and_bit()
1977 #define RV1126_DRV_PMU_OFFSET		0x20
1978 #define RV1126_DRV_GRF_GPIO1A0_OFFSET		0x10090
1990 	if (bank->bank_num == 0) {  in rv1126_calc_drv_reg_and_bit()
1995 			*reg -= 0x4;  in rv1126_calc_drv_reg_and_bit()
2013 #define RV1126_SCHMITT_PMU_OFFSET		0x60
2014 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET		0x10188
2027 	if (bank->bank_num == 0) {  in rv1126_calc_schmitt_reg_and_bit()
2033 			return 0;  in rv1126_calc_schmitt_reg_and_bit()
2047 	return 0;  in rv1126_calc_schmitt_reg_and_bit()
2050 #define RK1808_PULL_PMU_OFFSET		0x10
2051 #define RK1808_PULL_GRF_OFFSET		0x80
2063 	if (bank->bank_num == 0) {  in rk1808_calc_pull_reg_and_bit()
2076 #define RK1808_DRV_PMU_OFFSET		0x20
2077 #define RK1808_DRV_GRF_OFFSET		0x140
2089 	if (bank->bank_num == 0) {  in rk1808_calc_drv_reg_and_bit()
2102 #define RK1808_SCHMITT_PMU_OFFSET		0x0040
2103 #define RK1808_SCHMITT_GRF_OFFSET		0x0100
2114 	if (bank->bank_num == 0) {  in rk1808_calc_schmitt_reg_and_bit()
2125 	return 0;  in rk1808_calc_schmitt_reg_and_bit()
2128 #define RK2928_PULL_OFFSET		0x118
2146 #define RK3128_PULL_OFFSET	0x118
2162 #define RK3188_PULL_OFFSET		0x164
2166 #define RK3188_PULL_PMU_OFFSET		0x64
2175 	if (bank->bank_num == 0 && pin_num < 12) {  in rk3188_calc_pull_reg_and_bit()
2194 		 * pin in bits 1:0  in rk3188_calc_pull_reg_and_bit()
2201 #define RK3288_PULL_OFFSET		0x140
2209 	if (bank->bank_num == 0) {  in rk3288_calc_pull_reg_and_bit()
2221 		*reg -= 0x10;  in rk3288_calc_pull_reg_and_bit()
2230 #define RK3288_DRV_PMU_OFFSET		0x70
2231 #define RK3288_DRV_GRF_OFFSET		0x1c0
2243 	if (bank->bank_num == 0) {  in rk3288_calc_drv_reg_and_bit()
2255 		*reg -= 0x10;  in rk3288_calc_drv_reg_and_bit()
2264 #define RK3228_PULL_OFFSET		0x100
2281 #define RK3228_DRV_GRF_OFFSET		0x200
2298 #define RK3308_PULL_OFFSET		0xa0
2315 #define RK3308_DRV_GRF_OFFSET		0x100
2334 #define RK3308_SCHMITT_GRF_OFFSET	0x1a0
2350 	return 0;  in rk3308_calc_schmitt_reg_and_bit()
2353 #define RK3368_PULL_GRF_OFFSET		0x100
2354 #define RK3368_PULL_PMU_OFFSET		0x10
2363 	if (bank->bank_num == 0) {  in rk3368_calc_pull_reg_and_bit()
2375 		*reg -= 0x10;  in rk3368_calc_pull_reg_and_bit()
2384 #define RK3368_DRV_PMU_OFFSET		0x20
2385 #define RK3368_DRV_GRF_OFFSET		0x200
2394 	if (bank->bank_num == 0) {  in rk3368_calc_drv_reg_and_bit()
2406 		*reg -= 0x10;  in rk3368_calc_drv_reg_and_bit()
2415 #define RK3399_PULL_GRF_OFFSET		0xe040
2416 #define RK3399_PULL_PMU_OFFSET		0x40
2426 	if ((bank->bank_num == 0) || (bank->bank_num == 1)) {  in rk3399_calc_pull_reg_and_bit()
2440 		*reg -= 0x20;  in rk3399_calc_pull_reg_and_bit()
2457 	if ((bank->bank_num == 0) || (bank->bank_num == 1))  in rk3399_calc_drv_reg_and_bit()
2470 #define RK3308_SLEW_RATE_GRF_OFFSET		0x150
2497 	{ 0, 2, 4, 6, 6, 8, 10, 12 }
2525 	for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {  in rockchip_set_drive_perpin()
2529 		} else if (rockchip_perpin_drv_list[drv_type][i] < 0) {  in rockchip_set_drive_perpin()
2535 	if (ret < 0) {  in rockchip_set_drive_perpin()
2545 			data = 0x3 << (bit + 16);  in rockchip_set_drive_perpin()
2546 			data |= ((regval & 0x3) << bit);  in rockchip_set_drive_perpin()
2549 			if (ret < 0)  in rockchip_set_drive_perpin()
2553 			data = BIT(bit + 16) | (((regval > 3) ? 1 : 0) << bit);  in rockchip_set_drive_perpin()
2564 		case 0 ... 12:  in rockchip_set_drive_perpin()
2570 			 * over 2 registers, the bit data[15] contains bit 0  in rockchip_set_drive_perpin()
2571 			 * of the value while temp[1:0] contains bits 2 and 1  in rockchip_set_drive_perpin()
2573 			data = (ret & 0x1) << 15;  in rockchip_set_drive_perpin()
2574 			temp = (ret >> 0x1) & 0x3;  in rockchip_set_drive_perpin()
2581 			temp |= (0x3 << 16);  in rockchip_set_drive_perpin()
2582 			reg += 0x4;  in rockchip_set_drive_perpin()
2652 		return pull ? -EINVAL : 0;  in rockchip_set_pull()
2679 		for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);  in rockchip_set_pull()
2687 		if (ret < 0) {  in rockchip_set_pull()
2714 #define RK3328_SCHMITT_GRF_OFFSET		0x380
2730 	return 0;  in rk3328_calc_schmitt_reg_and_bit()
2756 #define PX30_SLEW_RATE_PMU_OFFSET		0x30
2757 #define PX30_SLEW_RATE_GRF_OFFSET		0x90
2770 	if (bank->bank_num == 0) {  in px30_calc_slew_rate_reg_and_bit()
2783 	return 0;  in px30_calc_slew_rate_reg_and_bit()
2872 		if (rc < 0)  in rockchip_pinconf_set()
2881 		if (rc < 0)  in rockchip_pinconf_set()
2891 		if (rc < 0)  in rockchip_pinconf_set()
2899 	return 0;  in rockchip_pinconf_set()
2903 	{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
2904 	{ "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
2907 	{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
2909 	{ "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
2910 	{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
2912 	{ "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
2931 	*default_value = 0;  in rockchip_pinconf_prop_name_to_param()
2956 	if (count < 0) {
2968 	for (i = 0; i < count; i++)
2971 	for (i = 0; i < (count >> 2); i++) {
2972 		bank = cells[4 * i + 0];
3004 			if (param < 0)
3022 	return 0;
3067 	nr_pins = 0;
3068 	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3069 		int bank_pins = 0;
3076 		for (j = 0; j < 4; j++) {
3085 			if (iom->offset >= 0) {
3097 			if (drv->offset >= 0) {
3107 			debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3141 		for (j = 0; j < ctrl->niomux_recalced; j++) {
3142 			int pin = 0;
3151 		for (j = 0; j < ctrl->niomux_routes; j++) {
3152 			int pin = 0;
3169 #define RK3308B_GRF_SOC_CON13			0x608
3170 #define RK3308B_GRF_SOC_CON15			0x610
3203 	return 0;
3212 	int ret = 0;
3257 	return 0;
3261 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3289 	.grf_mux_offset		= 0x0,
3290 	.pmu_mux_offset		= 0x0,
3300 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3304 	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3305 	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3306 	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3315 	.grf_mux_offset		= 0x10,
3316 	.pmu_mux_offset		= 0x0,
3325 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
3335 			     0x10010, 0x10018, 0x10020, 0x10028),
3347 			     IOMUX_WIDTH_4BIT, 0, 0, 0),
3356 	.grf_mux_offset		= 0x10004, /* mux offset from GPIO0_D0 */
3357 	.pmu_mux_offset		= 0x0,
3368 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
3403 	.grf_mux_offset		= 0x0,
3404 	.pmu_mux_offset		= 0x0,
3411 	PIN_BANK(0, 32, "gpio0"),
3423 	.grf_mux_offset		= 0xa8,
3428 	PIN_BANK(0, 32, "gpio0"),
3439 	.grf_mux_offset		= 0xa8,
3444 	PIN_BANK(0, 32, "gpio0"),
3458 	.grf_mux_offset		= 0xa8,
3463 	PIN_BANK(0, 32, "gpio0"),
3475 	.grf_mux_offset		= 0x60,
3479 	PIN_BANK(0, 32, "gpio0"),
3491 	.grf_mux_offset		= 0xa8,
3500 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3512 	.grf_mux_offset		= 0x60,
3517 	PIN_BANK(0, 32, "gpio0"),
3529 	.grf_mux_offset		= 0x0,
3537 	PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0",
3545 				      0,
3549 				      0
3554 					     0
3556 	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3557 	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3560 					     0,
3561 					     0
3564 					     0,
3565 					     0,
3568 	PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3569 	PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3570 					     0,
3583 	.grf_mux_offset		= 0x0,
3584 	.pmu_mux_offset		= 0x84,
3592 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT,
3620 		.grf_mux_offset		= 0x0,
3636 	.grf_mux_offset		= 0x0,
3648 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3649 	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3650 	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3653 			     0),
3657 			     0,
3658 			     0),
3667 	.grf_mux_offset		= 0x0,
3678 	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3694 	.grf_mux_offset		= 0x0,
3695 	.pmu_mux_offset		= 0x0,
3701 	PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3710 							 0x80,
3711 							 0x88,
3727 					0xa0,
3728 					0xa8,
3729 					0xb0,
3730 					0xb8
3759 	.grf_mux_offset		= 0xe000,
3760 	.pmu_mux_offset		= 0x0,
3761 	.grf_drv_offset		= 0xe100,
3762 	.pmu_drv_offset		= 0x80,