2  * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3  * Written by Jean-Jacques Hiblot  <jjhiblot@ti.com>
5  * SPDX-License-Identifier:	GPL-2.0+
11 #include <generic-phy.h>
14 #include <syscon.h>
44 /* PHY POWER CONTROL Register */
94 	struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;  in omap_pipe3_get_dpll_params()
98 	for (; dpll_map->rate; dpll_map++) {  in omap_pipe3_get_dpll_params()
99 		if (rate == dpll_map->rate)  in omap_pipe3_get_dpll_params()
100 			return &dpll_map->params;  in omap_pipe3_get_dpll_params()
115 		val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);  in omap_pipe3_wait_lock()
118 	} while (--timeout);  in omap_pipe3_wait_lock()
122 		return -EBUSY;  in omap_pipe3_wait_lock()
136 		return -EINVAL;  in omap_pipe3_dpll_program()
139 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);  in omap_pipe3_dpll_program()
141 	val |= dpll_params->n << PLL_REGN_SHIFT;  in omap_pipe3_dpll_program()
142 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);  in omap_pipe3_dpll_program()
144 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);  in omap_pipe3_dpll_program()
146 	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;  in omap_pipe3_dpll_program()
147 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);  in omap_pipe3_dpll_program()
149 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);  in omap_pipe3_dpll_program()
151 	val |= dpll_params->m << PLL_REGM_SHIFT;  in omap_pipe3_dpll_program()
152 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);  in omap_pipe3_dpll_program()
154 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION4);  in omap_pipe3_dpll_program()
156 	val |= dpll_params->mf << PLL_REGM_F_SHIFT;  in omap_pipe3_dpll_program()
157 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION4, val);  in omap_pipe3_dpll_program()
159 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION3);  in omap_pipe3_dpll_program()
161 	val |= dpll_params->sd << PLL_SD_SHIFT;  in omap_pipe3_dpll_program()
162 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION3, val);  in omap_pipe3_dpll_program()
164 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_GO, SET_PLL_GO);  in omap_pipe3_dpll_program()
173 	val = readl(pipe3->power_reg);  in omap_control_pipe3_power()
191 	writel(val, pipe3->power_reg);  in omap_control_pipe3_power()
194 static int pipe3_init(struct phy *phy)  in pipe3_init()  argument
198 	struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);  in pipe3_init()
201 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);  in pipe3_init()
208 		val = omap_pipe3_readl(pipe3->pll_ctrl_base,  in pipe3_init()
212 			omap_pipe3_writel(pipe3->pll_ctrl_base,  in pipe3_init()
222 static int pipe3_power_on(struct phy *phy)  in pipe3_power_on()  argument
224 	struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);  in pipe3_power_on()
226 	/* Power up the PHY */  in pipe3_power_on()
232 static int pipe3_power_off(struct phy *phy)  in pipe3_power_off()  argument
234 	struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);  in pipe3_power_off()
236 	/* Power down the PHY */  in pipe3_power_off()
242 static int pipe3_exit(struct phy *phy)  in pipe3_exit()  argument
246 	struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);  in pipe3_exit()
248 	pipe3_power_off(phy);  in pipe3_exit()
251 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);  in pipe3_exit()
253 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);  in pipe3_exit()
255 	/* wait for LDO and Oscillator to power down */  in pipe3_exit()
258 		val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);  in pipe3_exit()
261 	} while (--timeout);  in pipe3_exit()
264 		pr_err("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",  in pipe3_exit()
266 		return -EBUSY;  in pipe3_exit()
269 	val = readl(pipe3->pll_reset_reg);  in pipe3_exit()
270 	writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);  in pipe3_exit()
272 	writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);  in pipe3_exit()
278 	struct udevice *syscon;  in get_reg()  local
285 					   name, &syscon);  in get_reg()
287 		pr_err("unable to find syscon device for %s (%d)\n",  in get_reg()
292 	regmap = syscon_get_regmap(syscon);  in get_reg()
299 	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), name,  in get_reg()
322 		return -EINVAL;  in pipe3_phy_probe()
325 	pipe3->pll_ctrl_base = map_physmem(addr, sz, MAP_NOCACHE);  in pipe3_phy_probe()
326 	if (!pipe3->pll_ctrl_base) {  in pipe3_phy_probe()
328 		return -EINVAL;  in pipe3_phy_probe()
331 	pipe3->power_reg = get_reg(dev, "syscon-phy-power");  in pipe3_phy_probe()
332 	if (!pipe3->power_reg)  in pipe3_phy_probe()
333 		return -EINVAL;  in pipe3_phy_probe()
335 	pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");  in pipe3_phy_probe()
336 	if (!pipe3->pll_reset_reg)  in pipe3_phy_probe()
337 		return -EINVAL;  in pipe3_phy_probe()
339 	pipe3->dpll_map = (struct pipe3_dpll_map *)dev_get_driver_data(dev);  in pipe3_phy_probe()
355 	{ .compatible = "ti,phy-pipe3-sata", .data = (ulong)&dpll_map_sata },