96 	int (*combophy_init)(struct rockchip_udphy *udphy);
97 	int (*dp_phy_set_rate)(struct rockchip_udphy *udphy,
99 	int (*dp_phy_set_voltages)(struct rockchip_udphy *udphy,
101 	int (*dplane_enable)(struct rockchip_udphy *udphy, int dp_lanes);
102 	int (*dplane_select)(struct rockchip_udphy *udphy);
328 static int udphy_clk_init(struct rockchip_udphy *udphy, struct udevice *dev)  in udphy_clk_init()  argument
333 static int udphy_reset_init(struct rockchip_udphy *udphy, struct udevice *dev)  in udphy_reset_init()  argument
335 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_reset_init()
339 	udphy->rsts = devm_kcalloc(dev, cfg->num_rsts,  in udphy_reset_init()
340 				   sizeof(*udphy->rsts), GFP_KERNEL);  in udphy_reset_init()
341 	if (!udphy->rsts)  in udphy_reset_init()
347 		ret = reset_get_by_name(dev, name, &udphy->rsts[idx]);  in udphy_reset_init()
353 		reset_assert(&udphy->rsts[idx]);  in udphy_reset_init()
359 	devm_kfree(dev, udphy->rsts);  in udphy_reset_init()
375 static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name)  in udphy_reset_assert()  argument
377 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_reset_assert()
384 	return reset_assert(&udphy->rsts[idx]);  in udphy_reset_assert()
387 static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name)  in udphy_reset_deassert()  argument
389 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_reset_deassert()
396 	return reset_deassert(&udphy->rsts[idx]);  in udphy_reset_deassert()
399 static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable)  in udphy_u3_port_disable()  argument
401 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_u3_port_disable()
404 	preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;  in udphy_u3_port_disable()
405 	grfreg_write(udphy->usbgrf, preg, disable);  in udphy_u3_port_disable()
409 static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable)  in udphy_usb_bvalid_enable()  argument
411 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_usb_bvalid_enable()
413 	grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);  in udphy_usb_bvalid_enable()
414 	grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);  in udphy_usb_bvalid_enable()
452 static int udphy_dplane_select(struct rockchip_udphy *udphy)  in udphy_dplane_select()  argument
454 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_dplane_select()
457 		return cfg->dplane_select(udphy);  in udphy_dplane_select()
462 static int udphy_dplane_get(struct rockchip_udphy *udphy)  in udphy_dplane_get()  argument
466 	switch (udphy->mode) {  in udphy_dplane_get()
483 static int udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes)  in udphy_dplane_enable()  argument
485 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_dplane_enable()
489 		ret = cfg->dplane_enable(udphy, dp_lanes);  in udphy_dplane_enable()
496 static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy)  in upphy_set_typec_default_mapping()  argument
498 	if (udphy->flip) {  in upphy_set_typec_default_mapping()
499 		udphy->dp_lane_sel[0] = 0;  in upphy_set_typec_default_mapping()
500 		udphy->dp_lane_sel[1] = 1;  in upphy_set_typec_default_mapping()
501 		udphy->dp_lane_sel[2] = 3;  in upphy_set_typec_default_mapping()
502 		udphy->dp_lane_sel[3] = 2;  in upphy_set_typec_default_mapping()
503 		udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;  in upphy_set_typec_default_mapping()
504 		udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;  in upphy_set_typec_default_mapping()
505 		udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;  in upphy_set_typec_default_mapping()
506 		udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;  in upphy_set_typec_default_mapping()
507 		udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;  in upphy_set_typec_default_mapping()
508 		udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;  in upphy_set_typec_default_mapping()
510 		udphy->dp_lane_sel[0] = 2;  in upphy_set_typec_default_mapping()
511 		udphy->dp_lane_sel[1] = 3;  in upphy_set_typec_default_mapping()
512 		udphy->dp_lane_sel[2] = 1;  in upphy_set_typec_default_mapping()
513 		udphy->dp_lane_sel[3] = 0;  in upphy_set_typec_default_mapping()
514 		udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;  in upphy_set_typec_default_mapping()
515 		udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;  in upphy_set_typec_default_mapping()
516 		udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;  in upphy_set_typec_default_mapping()
517 		udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;  in upphy_set_typec_default_mapping()
518 		udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;  in upphy_set_typec_default_mapping()
519 		udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;  in upphy_set_typec_default_mapping()
522 	udphy->mode = UDPHY_MODE_DP_USB;  in upphy_set_typec_default_mapping()
527 static int udphy_setup(struct rockchip_udphy *udphy)  in udphy_setup()  argument
529 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_setup()
533 		ret = cfg->combophy_init(udphy);  in udphy_setup()
535 			dev_err(udphy->dev, "failed to init combophy\n");  in udphy_setup()
541 static int udphy_disable(struct rockchip_udphy *udphy)  in udphy_disable()  argument
543 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in udphy_disable()
547 		reset_assert(&udphy->rsts[i]);  in udphy_disable()
552 static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct udevice *dev)  in udphy_parse_lane_mux_data()  argument
561 		udphy->mode = UDPHY_MODE_USB;  in udphy_parse_lane_mux_data()
572 	ret = of_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes);  in udphy_parse_lane_mux_data()
581 		if (udphy->dp_lane_sel[i] > 3) {  in udphy_parse_lane_mux_data()
586 		udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;  in udphy_parse_lane_mux_data()
589 			if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {  in udphy_parse_lane_mux_data()
596 	udphy->mode = UDPHY_MODE_DP;  in udphy_parse_lane_mux_data()
598 		udphy->mode |= UDPHY_MODE_USB;  in udphy_parse_lane_mux_data()
599 		udphy->flip = udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP ? true : false;  in udphy_parse_lane_mux_data()
605 static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev)  in udphy_parse_dt()  argument
610 	udphy->u2phygrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,u2phy-grf");  in udphy_parse_dt()
611 	if (IS_ERR(udphy->u2phygrf)) {  in udphy_parse_dt()
612 		if (PTR_ERR(udphy->u2phygrf) == -ENODEV) {  in udphy_parse_dt()
614 			udphy->u2phygrf = NULL;  in udphy_parse_dt()
616 			return PTR_ERR(udphy->u2phygrf);  in udphy_parse_dt()
620 	udphy->udphygrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,usbdpphy-grf");  in udphy_parse_dt()
621 	if (IS_ERR(udphy->udphygrf)) {  in udphy_parse_dt()
622 		if (PTR_ERR(udphy->udphygrf) == -ENODEV) {  in udphy_parse_dt()
624 			udphy->udphygrf = NULL;  in udphy_parse_dt()
626 			return PTR_ERR(udphy->udphygrf);  in udphy_parse_dt()
630 	udphy->usbgrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,usb-grf");  in udphy_parse_dt()
631 	if (IS_ERR(udphy->usbgrf)) {  in udphy_parse_dt()
632 		if (PTR_ERR(udphy->usbgrf) == -ENODEV) {  in udphy_parse_dt()
634 			udphy->usbgrf = NULL;  in udphy_parse_dt()
636 			return PTR_ERR(udphy->usbgrf);  in udphy_parse_dt()
640 	udphy->vogrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,vo-grf");  in udphy_parse_dt()
641 	if (IS_ERR(udphy->vogrf)) {  in udphy_parse_dt()
642 		if (PTR_ERR(udphy->vogrf) == -ENODEV) {  in udphy_parse_dt()
644 			udphy->vogrf = NULL;  in udphy_parse_dt()
646 			return PTR_ERR(udphy->vogrf);  in udphy_parse_dt()
650 	ret = udphy_parse_lane_mux_data(udphy, dev);  in udphy_parse_dt()
656 		udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false;  in udphy_parse_dt()
659 	ret = udphy_clk_init(udphy, dev);  in udphy_parse_dt()
663 	ret = udphy_reset_init(udphy, dev);  in udphy_parse_dt()
670 static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)  in udphy_power_on()  argument
674 	if (!(udphy->mode & mode)) {  in udphy_power_on()
675 		printf("%s: mode 0x%02x is not support\n", udphy->dev->name,  in udphy_power_on()
680 	if (udphy->status == UDPHY_MODE_NONE) {  in udphy_power_on()
681 		udphy->mode_change = false;  in udphy_power_on()
682 		ret = udphy_setup(udphy);  in udphy_power_on()
686 		if (udphy->mode & UDPHY_MODE_USB)  in udphy_power_on()
687 			udphy_u3_port_disable(udphy, false);  in udphy_power_on()
688 	} else if (udphy->mode_change) {  in udphy_power_on()
689 		udphy->mode_change = false;  in udphy_power_on()
690 		udphy->status = UDPHY_MODE_NONE;  in udphy_power_on()
691 		if (udphy->mode == UDPHY_MODE_DP)  in udphy_power_on()
692 			udphy_u3_port_disable(udphy, true);  in udphy_power_on()
694 		ret = udphy_disable(udphy);  in udphy_power_on()
697 		ret = udphy_setup(udphy);  in udphy_power_on()
702 	udphy->status |= mode;  in udphy_power_on()
707 static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)  in udphy_power_off()  argument
711 	if (!(udphy->mode & mode)) {  in udphy_power_off()
712 		dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);  in udphy_power_off()
716 	if (!udphy->status)  in udphy_power_off()
719 	udphy->status &= ~mode;  in udphy_power_off()
721 	if (udphy->status == UDPHY_MODE_NONE) {  in udphy_power_off()
722 		ret = udphy_disable(udphy);  in udphy_power_off()
733 	struct rockchip_udphy *udphy = dev_get_priv(parent);  in rockchip_dpphy_power_on()  local
736 	dp_lanes = udphy_dplane_get(udphy);  in rockchip_dpphy_power_on()
738 	phy->attrs.max_link_rate = udphy->max_link_rate;  in rockchip_dpphy_power_on()
740 	ret = udphy_power_on(udphy, UDPHY_MODE_DP);  in rockchip_dpphy_power_on()
744 	ret = udphy_dplane_enable(udphy, dp_lanes);  in rockchip_dpphy_power_on()
748 	return udphy_dplane_select(udphy);  in rockchip_dpphy_power_on()
754 	struct rockchip_udphy *udphy = dev_get_priv(parent);  in rockchip_dpphy_power_off()  local
757 	ret = udphy_dplane_enable(udphy, 0);  in rockchip_dpphy_power_off()
761 	return udphy_power_off(udphy, UDPHY_MODE_DP);  in rockchip_dpphy_power_off()
764 static int rockchip_dpphy_verify_config(struct rockchip_udphy *udphy,  in rockchip_dpphy_verify_config()  argument
820 	struct rockchip_udphy *udphy = dev_get_priv(parent);  in rockchip_dpphy_configure()  local
821 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in rockchip_dpphy_configure()
824 	ret = rockchip_dpphy_verify_config(udphy, &opts->dp);  in rockchip_dpphy_configure()
829 		ret = cfg->dp_phy_set_rate(udphy, &opts->dp);  in rockchip_dpphy_configure()
832 			       udphy->dev->name);  in rockchip_dpphy_configure()
838 		ret = cfg->dp_phy_set_voltages(udphy, &opts->dp);  in rockchip_dpphy_configure()
841 			       udphy->dev->name);  in rockchip_dpphy_configure()
858 	struct rockchip_udphy *udphy = dev_get_priv(parent);  in rockchip_u3phy_init()  local
861 	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {  in rockchip_u3phy_init()
862 		udphy_u3_port_disable(udphy, true);  in rockchip_u3phy_init()
866 	return udphy_power_on(udphy, UDPHY_MODE_USB);  in rockchip_u3phy_init()
872 	struct rockchip_udphy *udphy = dev_get_priv(parent);  in rockchip_u3phy_exit()  local
875 	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)  in rockchip_u3phy_exit()
878 	return udphy_power_off(udphy, UDPHY_MODE_USB);  in rockchip_u3phy_exit()
889 	struct rockchip_udphy *udphy;  in rockchip_u3phy_uboot_init()  local
901 	udphy = dev_get_priv(udev->parent);  in rockchip_u3phy_uboot_init()
902 	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {  in rockchip_u3phy_uboot_init()
903 		udphy_u3_port_disable(udphy, true);  in rockchip_u3phy_uboot_init()
907 	return udphy_power_on(udphy, UDPHY_MODE_USB);  in rockchip_u3phy_uboot_init()
913 	struct rockchip_udphy *udphy = dev_get_priv(dev);  in rockchip_udphy_probe()  local
917 	udphy->dev = dev;  in rockchip_udphy_probe()
922 	udphy->id = id;  in rockchip_udphy_probe()
929 	udphy->cfgs = phy_cfgs;  in rockchip_udphy_probe()
931 	ret = regmap_init_mem(dev, &udphy->pma_regmap);  in rockchip_udphy_probe()
934 	udphy->pma_regmap->base += UDPHY_PMA;  in rockchip_udphy_probe()
936 	ret = udphy_parse_dt(udphy, dev);  in rockchip_udphy_probe()
983 static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy)  in rk3588_udphy_refclk_set()  argument
988 	ret = __regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_24m_refclk_cfg,  in rk3588_udphy_refclk_set()
996 static int rk3588_udphy_status_check(struct rockchip_udphy *udphy)  in rk3588_udphy_status_check()  argument
1002 	if (udphy->mode & UDPHY_MODE_USB) {  in rk3588_udphy_status_check()
1003 		ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET,  in rk3588_udphy_status_check()
1007 			dev_err(udphy->dev, "cmn ana lcpll lock timeout\n");  in rk3588_udphy_status_check()
1012 	if (udphy->mode & UDPHY_MODE_USB) {  in rk3588_udphy_status_check()
1013 		if (!udphy->flip) {  in rk3588_udphy_status_check()
1014 			ret = regmap_read_poll_timeout(udphy->pma_regmap,  in rk3588_udphy_status_check()
1019 				dev_notice(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");  in rk3588_udphy_status_check()
1021 			ret = regmap_read_poll_timeout(udphy->pma_regmap,  in rk3588_udphy_status_check()
1026 				dev_notice(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");  in rk3588_udphy_status_check()
1033 static int rk3588_udphy_init(struct rockchip_udphy *udphy)  in rk3588_udphy_init()  argument
1035 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in rk3588_udphy_init()
1039 	if (udphy->mode & UDPHY_MODE_USB)  in rk3588_udphy_init()
1040 		grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true);  in rk3588_udphy_init()
1043 	grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true);  in rk3588_udphy_init()
1045 	udphy_reset_deassert(udphy, "pma_apb");  in rk3588_udphy_init()
1046 	udphy_reset_deassert(udphy, "pcs_apb");  in rk3588_udphy_init()
1049 	ret = __regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_init_sequence,  in rk3588_udphy_init()
1052 		dev_err(udphy->dev, "init sequence set error %d\n", ret);  in rk3588_udphy_init()
1056 	ret = rk3588_udphy_refclk_set(udphy);  in rk3588_udphy_init()
1058 		dev_err(udphy->dev, "refclk set error %d\n", ret);  in rk3588_udphy_init()
1063 	regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET,  in rk3588_udphy_init()
1065 			   FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) |  in rk3588_udphy_init()
1066 			   FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) |  in rk3588_udphy_init()
1067 			   FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) |  in rk3588_udphy_init()
1068 			   FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) |  in rk3588_udphy_init()
1072 	if (udphy->mode & UDPHY_MODE_USB)  in rk3588_udphy_init()
1073 		udphy_reset_deassert(udphy, "init");  in rk3588_udphy_init()
1075 	if (udphy->mode & UDPHY_MODE_DP) {  in rk3588_udphy_init()
1076 		regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,  in rk3588_udphy_init()
1084 	if (udphy->mode & UDPHY_MODE_USB) {  in rk3588_udphy_init()
1085 		udphy_reset_deassert(udphy, "cmn");  in rk3588_udphy_init()
1086 		udphy_reset_deassert(udphy, "lane");  in rk3588_udphy_init()
1090 	ret = rk3588_udphy_status_check(udphy);  in rk3588_udphy_init()
1097 	udphy_reset_assert(udphy, "init");  in rk3588_udphy_init()
1098 	udphy_reset_assert(udphy, "cmn");  in rk3588_udphy_init()
1099 	udphy_reset_assert(udphy, "lane");  in rk3588_udphy_init()
1102 	udphy_reset_assert(udphy, "pma_apb");  in rk3588_udphy_init()
1103 	udphy_reset_assert(udphy, "pcs_apb");  in rk3588_udphy_init()
1107 static int rk3588_udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes)  in rk3588_udphy_dplane_enable()  argument
1113 		val |= BIT(udphy->dp_lane_sel[i]);  in rk3588_udphy_dplane_enable()
1115 	regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL,  in rk3588_udphy_dplane_enable()
1119 		regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,  in rk3588_udphy_dplane_enable()
1125 static int rk3588_udphy_dplane_select(struct rockchip_udphy *udphy)  in rk3588_udphy_dplane_select()  argument
1129 	switch (udphy->mode) {  in rk3588_udphy_dplane_select()
1131 		value |= 2 << udphy->dp_lane_sel[2] * 2;  in rk3588_udphy_dplane_select()
1132 		value |= 3 << udphy->dp_lane_sel[3] * 2;  in rk3588_udphy_dplane_select()
1134 		value |= 0 << udphy->dp_lane_sel[0] * 2;  in rk3588_udphy_dplane_select()
1135 		value |= 1 << udphy->dp_lane_sel[1] * 2;  in rk3588_udphy_dplane_select()
1143 	regmap_write(udphy->vogrf, udphy->id ? RK3588_GRF_VO0_CON2 : RK3588_GRF_VO0_CON0,  in rk3588_udphy_dplane_select()
1145 		     FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) |  in rk3588_udphy_dplane_select()
1146 		     FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);  in rk3588_udphy_dplane_select()
1151 static int rk3588_dp_phy_set_rate(struct rockchip_udphy *udphy,  in rk3588_dp_phy_set_rate()  argument
1157 	regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,  in rk3588_dp_phy_set_rate()
1162 		udphy->bw = DP_BW_RBR;  in rk3588_dp_phy_set_rate()
1165 		udphy->bw = DP_BW_HBR;  in rk3588_dp_phy_set_rate()
1168 		udphy->bw = DP_BW_HBR2;  in rk3588_dp_phy_set_rate()
1171 		udphy->bw = DP_BW_HBR3;  in rk3588_dp_phy_set_rate()
1177 	regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW,  in rk3588_dp_phy_set_rate()
1178 			   FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw));  in rk3588_dp_phy_set_rate()
1179 	regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN,  in rk3588_dp_phy_set_rate()
1181 	regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN,  in rk3588_dp_phy_set_rate()
1184 	ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val,  in rk3588_dp_phy_set_rate()
1196 static void rk3588_dp_phy_set_voltage(struct rockchip_udphy *udphy, u8 bw,  in rk3588_dp_phy_set_voltage()  argument
1201 	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;  in rk3588_dp_phy_set_voltage()
1206 	regmap_write(udphy->pma_regmap, 0x0810 + offset, val);  in rk3588_dp_phy_set_voltage()
1209 	regmap_write(udphy->pma_regmap, 0x0814 + offset, val);  in rk3588_dp_phy_set_voltage()
1212 	regmap_write(udphy->pma_regmap, 0x0818 + offset, val);  in rk3588_dp_phy_set_voltage()
1215 	regmap_write(udphy->pma_regmap, 0x081c + offset, val);  in rk3588_dp_phy_set_voltage()
1218 static int rk3588_dp_phy_set_voltages(struct rockchip_udphy *udphy,  in rk3588_dp_phy_set_voltages()  argument
1224 		lane = udphy->dp_lane_sel[i];  in rk3588_dp_phy_set_voltages()
1228 			regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane),  in rk3588_dp_phy_set_voltages()
1231 						      udphy->lane_mux_sel[lane]));  in rk3588_dp_phy_set_voltages()
1235 			regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane),  in rk3588_dp_phy_set_voltages()
1241 		rk3588_dp_phy_set_voltage(udphy, udphy->bw, dp->voltage[i], dp->pre[i], lane);  in rk3588_dp_phy_set_voltages()
1249 	struct rockchip_udphy *udphy = dev_get_priv(dev->parent);  in rockchip_dpphy_probe()  local
1265 	udphy->max_link_rate = max_link_rate;  in rockchip_dpphy_probe()